Nanoparticle Synthesis & Applications – Page 58

Compact Modelling of High-Voltage LDMOS Devices

Aarts A.C.T., van der Hout R., van Langevelde R., van der Hout R., van Langevelde R., Scholten A.J., Willemsen M.B., Klaassen D.B.M., Philips Research Laboratories, NE

In this paper various modelling approaches for Laterally Double-Di used MOS (LDMOS) devices are discussed. Characterisation results for the new compact LDMOS model called MOS Model 20 are presented. Measurements of the dc-current, its conductances [...]

Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices

Watts J., Lu N., Bittner C., Grundon S., Oppold J., IBM, US

In addition to the overall range of circuit characteristics expected from process variation the circuit designer needs to know how closely different circuit element will track one another. We describe a new methodology for modeling [...]

A Study of Figures of Merit for the High Frequency Behavior of MOSFETs in RF IC Applications

Cheng Y., Siliconlinx, US

This paper is to review important device parameters as the figures of merit (FOM) to understand the device characteristics for analog/RF applications. These FOM should be characterized and evaluated in technology development and model generation [...]

Challenges in Compact Modeling for RF and Microwave Applications

Niknejad A., Dunga M., Heydari B., Wan H., Lin C.H., Emami S., Doan C., Xi X., He J., Heydari B., Hu C., University of California at Berkeley, US

Commercial CMOS chips routinely operate at frequencies up to 5 GHz and exciting new opportunities exists in higher frequency bands such as 3-10 GHz, 17 GHz, 24 GHz, and 60 GHz. Many research groups have [...]

RF-MOSFET Model Parameter Extraction with HiSIM

Miura-Mattausch M., Sadachika N., Murakawa M., Mimura S., Higuchi T., Itoh K., Inagaki R., Iguchi Y., Hiroshima University, JP

This paper discusses a feasibility of an automatic parameter extraction method with the GA (Genetic Algorithm) for surface-potential-based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model), where all device characteristics are described as functions of the [...]

Analytic Solution for the Drain Current of Undoped Symmetric Dual-Gate MOSFET

Ortiz-Conde A., García-Sánchez F.J., Malobabic S., Muci J., Universidad Simón Bolívar, VE

A potential-based drain current model is presented for nanoscale undoped-body symmetric double gate MOSFETs. It is based on a fully coherent physical description and consists of a single analytic equation that includes both drift and [...]

Physics-Based, Non-Charge-Sheet Compact Modeling of Double-Gate MOSFETs

Lu H., Taur Y., University of California at San Diego, US

A physics-based, non-charge-sheet analytic potential model is presented for undoped (or lightly doped) Double Gate (DG) MOSFETs. With only the mobile charge term included, Poisson’s equation is rigorously solved and the electrostatic potential is derived [...]

Compact Model of Multiple-gate SOI MOSFETs

Iñiguez B., Hamid H.A., Jiménez D., Roig J., Universitat Rovira i Virgili, ES

In this work we present compact modelling schemes, for the undoped nanoscale multiple-gate MOSFET, suitable for design and projection of these devices. The proposed models have a physical basis and assume well-tempered multiple-gate MOSFETs; i.e., [...]

Modeling and Characterization of High Frequency Effects in ULSI Interconnects

Arora N.D., Song L., Cadence Design Systems, US

This paper discusses the accurate modeling of resistance R, inductance L and capacitance C in sub-100nm process node and their impacts on high frequency effects such as delay, crosstalk, and power/ground bounce. Models of interconnect [...]

Correlated Noise Modeling and Simulation

McAndrew C., Coram G., Blaum A., Pilloud O., Freescale Semiconductor, US

This paper addresses several issues in noise modeling and simulation. It shows how correlated noise can be implemented in Verilog-A, and presents a new and simple technique to simulate the noise correlation coefficient using only [...]