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HomeTopicsCompact Modeling

Topic: Compact Modeling

Interface-trap Charges on Recombination DC Current-Voltage Characteristics in MOS transistors

Chen Z., Jie B.B., Sah C-T, Nanyang Technological University, SG
The interface traps and trapped charges along the surface channel region are generated during transistor stress or operation and primarily responsible for the changes of device properties. The threshold voltage is varied by the generation [...]

MOSFET Compact Modeling Issues for Low Temperature (77 K – 200 K) Operation

Martin P., Cavelier M., Fascio R., Ghibaudo G., CEA/LETI/MINATEC, FR
Advanced compact models are evaluated for simulation of mixed analog-digital circuits working at low temperature (77 to 200 K). This evaluation is performed on a dual gate oxide CMOS technology with 0.18 µm / 1.8 [...]

Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices

Nakagawa T., Sekigawa T., Tsutsumi T., Liu Y., Hioki M., O’uchi S., Koike H., Electroinformatics Group, JP
We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two [...]

Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping

Hariharan V., Thakker R., Patil M.B., Vasi J., Rao V.R., IIT Bombay, IN
In this paper we present a completely closed-form inversion charge-based model for the drain current and conductance of a symmetric double-gate MOSFET based on the drift-diffusion transport mechanism, that takes into account vertical field mobility [...]

Neural Computational Approach for FinFET Modeling and Nano-Circuit Simulation

Alam M.S., Kranti A., Armstrong G.A., Z. H. College of Engineering & Technology, IN
FinFETs are very promising for low power, low voltage portable applications. For nano-circuit simulation, a suitable FinFET model is required. A behavioural model based on a neural network has been developed in this work and [...]

Compact Models for Double Gate MOSFET with Quantum Mechanical Effects using Lambert Function

Abebe H., Morris H., Cumberbatch E., Tyree V., University of Southern California, ISI, US
This paper is a continuation of the work we presented in the 2006 IEEE UGIM Proceedings. Iterative compact device models with quantum mechanical effects for a Double Gate (DG) MOSFET are presented using the Lambert [...]

Parameter Extraction for Advanced MOSFET Model using Particle Swarm Optimization

Thakker R.A., Patil M.B., Anil K.G., Indian Institute of Technology, IN
In the sub 100-nm regime, MOSFET parameter extraction has become a challenging task. Commonly used gradient based methods have many difficulties such as good initial guess requirement, singularities in objective functions, etc. Genetic Algorithm (GA), [...]

An Improved Impact Ionization Model for SOI Circuit Simulation

Xi X., Li F., Liu W., Tudor B., Wang P., Wang W., Liu W., Lee F., Wang P., Wang W., Subba N., Goo J-S, Synopsys, Inc., US
The impact ionization (II) model accuracy issue in industry standard SOI MOSFET is discussed in the paper. Based on Medici 2D simulation study, an improved impact ionization model is proposed which can capture the voltage [...]

Analytical Modelling and Performance Analysis of Double-Gate MOSFET-based Circuit Including Ballistic/quasi-ballistic Effects

Martinie S., CEA/LETI/MINATEC, FR
As the MOSFET continues to shrink rapidly, emerging physical phenomena, such as ballistic transport, have to be considered in the modelling and simulation of ultra-scaled devices. Future Double-Gate MOSFETs, designed with channel lengths in the [...]

Process Aware Compact Model Parameter Extraction for 45 nm Process

Karmarkar A.P., Dasarapu V.K., Saha A.R., Braun G., Krishnamurthy S., Lin X-W, Synopsys (India) Pvt. Ltd., IN
The current industry trends call for smaller devices and decreasing feature sizes with each technology node. The process variability has a significant impact on the device characteristics for deep sub-micron technologies because of the smaller [...]

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