Compact Modeling – Page 15 – TechConnect Briefs

High Voltage MOSFET’s Modeling Review

Ma Y., Jeng M-C, Liu Z., Cadence Design System, Inc., US

In this paper, different modeling solutions for HVMOS and LDMOS are discussed, current status of compact model development for HVMOS/LDMOS are reviewed. Macro models are widely used to model HVMOS and LDMOS devices. Different macro [...]

A Computationally Efficient Method for Evaluating Distortion in DG MOSFETs

Salazar R., Ortiz-Conde A., García-Sánchez F.J., Solid State Electronics Laboratory, VE

In this paper we have generalized the correlation between Integral Nonlinearity Function (INLF) and Total Harmonic Distortion (THD) of independently driven double -gate (IDDG) MOSFETs.

Explicit Short Channel Compact Model of Independent Double Gate Mosfet

Reyboz M., Rozeau O., Poiroux T., Martin P., Cavelier M., Jomaah J., CEA-LETI, FR

This paper describes an explicit short channel compact model of Independent Double Gate (IDG) MOSFET with undoped channel. The validity of this model is demonstrated by comparison with Atlas simulations. The model was implemented in [...]

Compact modeling of drain current in Independently Driven Double-Gate MOSFETs

Munteanu D., Autran J-L, Loussier X., Tintori O., L2MP-CNRS, FR

As CMOS scaling is approaching its limits, Double-Gate (DG) MOSFET is envisaged as a possible alternative to the conventional bulk MOSFET. In spite of excellent electrical performances due to its multiple conduction surfaces, conventional DG [...]

Impact of Gate Induced Drain Leakage and Impact Ionization Currents on Hysteresis Modeling of PD SOI Circuits

Chen Q., Suryagandh S., Goo J-S, An J.X., Thuruthiyil C., Icel A.B., Advanced Micro Devices, US

The impact of the gate induced drain leakage and impact ionization currents on hysteresis of PD FB SOI circuits is examined, and a physical understanding is provided. Measured silicon data from 90nm and 65nm PD [...]

Optimal Skew Corners for Compact Models

Lu N., IBM, US

We present an innovative approach to generate an optimal skew corner of a compact device model (e.g., a Spice model) for a single performance target, and to generate a common/optimal skew corner of a compact [...]

Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types

Park J-E, Park S-J, Liang C-H, Assenmacher J., Watts J., Park J-E, Park S-J, Wachnik R., IBM, US

MOSFET device of similar design but different threshold voltage are often built on a single chip. It is important to be able to simulate with a compact model the variation of such devices including the [...]

Modeling Process Variations Using a Compact Model

Murali R., Meindl J.D., Georgia Tech, US

Inclusion of manufacturing variations has become an important part of static timing analysis. Existing statistical timing analysis methods involve the use of time-consuming circuit simulations or use fit polynomials. Previous efforts at modeling parameter variations [...]

Modeling MOSFET Process Variation using PSP

Watts J.S., Lee Y.M., Park J-E, IBM, US

The PSP model has been extensively evaluated for it’s abililty accurately match IV and CV characteristics MOSFETs measured on a single die. This enables accurate prediction of circuit behavior for circuits made of transistors which [...]

Modeling of FET Flicker Noise and Impact of Technology Scaling

Chen C-Y, Liu Y., Cao S., Dutton R., Sato-Iwanaga J., Inoue A., Sorada H., Stanford University, US

Ongoing scaling of device dimensions, including the introduction of new channel materials and device structures, as well as the incorporation of novel gate-stack materials, has major implications on noise performance metrics. In particular, flicker noise [...]