Papers – Page 1052 – TechConnect Briefs

Breakdown in the Output Characteristics of Deep Submicron, a-Si:H TFTs

Colalongo L., Valdinoci M., Forunato G., Mariucci L., Rudan M., University of Bologna, IT

Purpose of this work is to investigate the breakdown in the output characteristics of short-channel (0.2-1.o ,um) amorphous silicon (a-Si:H) thin-film transistors (TFTs). Such effect which, in the case of a-Si:H devices, has been detected [...]

Simulation of Narrow-Width Effects in Sub-Half-Micron n-MOSFETs with LOCOS Isolation

Loiko K.V., Peidous I.V., Ho H-M, Lim D.H., Chartered Semiconductor Manufacturing Ltd., SG

The anomalous threshold voltage behavior of sub-halfmicron LOCOS-isolated n-MOSFETs is explained by the segregation of boron and narrow-mask effect of local oxidation. A novel approach to simulating narrow-width effects is proposed. It combines 2-D process [...]

Cellular Automata Studies of Vertical MOSFETs

Saraniti M., Wigger S., Zandler G., Formicone G., Goodnick S.M., Arizona State University, US

This paper presents an overview of the cellular automata (CA) method for semiconductor device simulation. The main advantages of the CA method over the Monte Carlo (MC) approach are presented, and limitations of its modeling [...]

A Physics-Based Characterized Model for an Ultrafast Planar Rectifier

Hossain Z., Fragale W., Simpson W., Dashney G., Motorola, Inc., US

This paper presents a characterized nodel for an ultrafast-recovery (UFR) rectifier based on the manufacturing processes and device structural geometry. The accuray of the developed model depends upon the proper selection of physical models and [...]

Hierarchical Approach to Simulation in a Vertical System for the TriCore Microcontroller

Salzmann C., Chesters E., Coelho P., Fu Y-C, Madala J., Reddy M., Wang F., Siemens Microelectronics, Inc., US

This paper describes a hiercihical functional verification system for a core-based system design which minimizes complexity in testbenches while maximizing flexibility in terms of number of clocks and system interfaces and reducing time-to-market. The verification [...]

Simulations of a New CMOS Compatible Method to Enhance the Breakdown Voltage of Highly-Doped Shallow PN Junctions

Pauchard A., Besse P.A., Popovic R.S., EPFL, CH

Avalanche breakdown often limits the working range of planar junction diodes in electronic circuits and in sensors. We present two-dimensional device simulation results (using MEDICI) of a novel CMOS compatible structure. It combines a floating [...]

Concurrent Process, Device and Integrated Circuit Development by Predictive Engineering for Smart Power Technologies

Bafleur M., Dinh T., Park H., Thoma R., Zirkle T., Wild A., LAAS/CNRS, FR

Predictive TCAD has been shown to be a powerful tool for the development of low voltage CMOS and VLSI memory technology development [1], [2] in which the main features of advanced p-channel and n-channel MOS [...]

The Influence of Space Quantization Effect on the Threshold Voltage, Inversion Layer and Total Gate Capacitance in Scaled Si-MOSFETs

Vasileska D., Ferry D.K., Arizona State University, US

We investigate the influence of poly-gate depletion on the inversion layer capacitance CinV, total gate capacitance CtOt and threshold voltage VT in scaled Si MOSFETs using both semiclassical (SC) and quantum-mechanical (QM) description of the [...]

FELLINI-A CAD Tool for the Design of Microsystems

Lang M., Glesner M., Darmstadt University of Technology, DE

This paper reports of the CAD-tool FELLINI, which supports the design of microsysfems on the lower levels of abstraction. FELLINI provides a bidirectional interface between the structural and the layout level. A Layout-to-FEM converter as [...]

DOPDEES/PMM: A System for Portable Model Description

Gencer A.H., Dunham S.T., Boston University, US

We have developed a multi-purpose partial differential equation solver, DOPDEES, which is capable of solving initial value problems in one spatial dimension using a finite differences method. The system of partial fferential equations is specified [...]