Papers – Page 14 – TechConnect Briefs

The Vision and Action Plan of the National Nanotechnology Initiative

Roco M., National Science Foundation, US

The vision of novel phenomena, unity in nature, and promise of the most efficient manufacturing length scale has been essential in establishing the multidisciplinary National Nanotechnology Initiative (NNI). The research opportunities and projections of their [...]

New Compact Model for Generation Drain Current Transients in Weak and Moderate Inversions of Submicron Floating-Body PD SOI MOSFETs

Ionescu A.M., Munteanu D., Swiss Federal Institute of Technology-EPFL, CH

In this paper, generation-type drain current transients, in advanced (down to 50nm gate-length) floating-body PD SOI MOSFETs are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for [...]

Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction

Chiah S.B., Zhou X., Lim K.Y., See A., Chan L., Nanyang Technological University, SG

This paper demonstrates a physically-based approach to parameter extraction of the compact Ids model we have developed for deep-submicron technology development. A two-iteration parameter-extraction scheme is described, which improves the previous one-iteration approach. Parameter calibration [...]

Compact Model for Manufacturing Design and Fluctuation Study

Lim K.Y., Zhou X., Chartered Semiconductor Manufacturing Ltd., SG

In this article, a physics based compact model [1, 2] has been used as a tool for manufacturing process variability study. Three critical end-of-line (EOL) measured electrical testing (ET) parameters, namely Vth, Ion and Ioff, [...]

Simulation Study of Non-Quasi Static Behaviour of MOS Transistors

Kumar D.V., Thakker R.A., Patil M.B., Rao V.R., Indian Institute of Technology - Bombay, IN

In this paper, we study the "non-quasi static" (NQS) behaviour of MOS transistors using an exact quasi static Look-up Table (LUT) [1] MOSFET model implemented in a general-purpose circuit simulator SEQUEL [2], device simulator ISE-TCAD [...]

A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling

Larcher L., Pavan P., Università di Modena e Reggio Emilia, IT

This paper presents for the first time a new approach to hot-carrier phenomena leading to an analytical model of both Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) currents. This model can be [...]

Month: April 2002

The Vision and Action Plan of the National Nanotechnology Initiative

New Compact Model for Generation Drain Current Transients in Weak and Moderate Inversions of Submicron Floating-Body PD SOI MOSFETs

Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction

Compact Model for Manufacturing Design and Fluctuation Study

Simulation Study of Non-Quasi Static Behaviour of MOS Transistors

A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling

Measurements and Modeling of Mobility in Ultra-Thin SOI

Methodology for Model Generation with Accuracy from DC to RF

How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics

Interconnect Modeling for High Speed Digital Circuits – the Role of RLC Coupling