This paper presents an example modeling flow for generating a RF CMOS model. Initially, the objectives of this modeling approach are analyzed. Then issues in test structure design are discussed. In the section of model generation, we cover the procedures of DC, AC, 1/f noise and RF modeling. We examine the issues related to measurement, parameter extraction, and optimization. We then focus our discussion on the issues related to advanced CMOS technology: gate tunneling current, measuring gate capacitance with high tunneling current, and de-embedding in s-parameter measurement. We present a method to determine the ratio, between drain and source, of the gate to channel tunneling current. We also briefly introduce the 1/f noise measurement system, which can do on wafer 1/f noise characterization. Finally, we present the fitted model results.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Published: April 22, 2002
Pages: 730 - 733
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling