The modelisation of capacitance and inductance of wires for timing and noise simulation of digital circuits is discussed. Different domains characterized by the length of the wires and the driving strength require different approximations in the representation of the parasitic parameters. A modelisation methodology for interconnect parasitics is emerging.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Published: April 22, 2002
Pages: 722 - 725
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling