Topic: Nanoelectronics
Sub-Threshold Electron Mobility in SOI-MESFETs
Micropower circuits use subthreshold MOSFETs that consume minimal power resulting from the combination of ultra-low drain currents (10-11 < Id < 10-5 A/µm) and small drain voltages required for saturation (Vd sat ~150-200mV). Unfortunately, sub-threshold [...]
Ab Initio Simulation on Mechanical and Electronic Properties of Nanostructures under Deformation
Nanostructures have been attracting attention because of their prominent properties, and their applications for novel devices with advanced functions have been attemted. Large stress and strain occur in local regions in materials with nanostructures owing [...]
Principles of Metallic Field Effect Transistor (METFET)
Rotkin S.V., Hess K., University of Illinois at Urbana-Champaign, Beckman Institute for Advanced Science and Technology, US
Field effect transistors in current use are semiconductor devices. The scaling trend to nanometer dimensions calls for ever higher doping and channel conductance of these devices. Ultimately one desires a conductance close to that of [...]
Hierarchical Simulation Approaches for the Design of Ultra-Fast Amplifier Circuits
Desai J., Aboud S., Chiney P., Osuch P., Branlard J., Goodnick S., Saraniti M., IIT/Rush University, US
In this work, the design and development of ultra-fast amplifier circuits is investigated using a combination of simulation tools, including PSPICE. A fully depleted SOI transistor is designed based on state-of-the-art fabricated devices. To calibrate [...]
A Technology-Independent Model for Nanoscale Logic Devices
In this paper we describe a class of technology-independent nano-device models, motivated from fundamental physical considerations, and give some examples of their applications in nanocomputer architecture and systems engineering. These models rest on recent insights [...]
Full-band Particle-based Simulation of Germanium-On-Insulator FETs
Beysserie S., Branlard J., Aboud S., Goodnick S.M., Thornton T., Saraniti M., Illinois Institute of Technology, US
We model and simulate novel fully depleted (FD) sub-50nm gate lengths MOSFET structures using a full-band particle simulator based on the Cellular Monte Carlo (CMC) method that provides an accurate transport model at the high [...]
Methodology for Prediction of Ultra Shallow Junction Resistivities Considering Uncertainties with a Genetic Algorithm Optimization
The accurate prediction of arsenic activation after spike annealing is mandatory for Ultra Shallow Junction (USJ) sheet resistance optimization for advanced NMOS transistors engineering. For the first time, we propose a fast and efficient methodology [...]
Impact of Quantum Mechanical Tunnelling on Off-leakage Current in Double-gate MOSFET using a Quantum Drift-diffusion Model
With the growing use of wireless electronics systems, off-state leakage current in MOSFETs appears as one of the major physical limitations. Measurements of quantum tunnel current between source-drain (S?D) have recently shown that it will [...]