SOI – Page 3 – TechConnect Briefs

Random Dopant Induced Fluctuations of Characteristics in Deep Sub-micron MOSFETs

Chou H-M, Lo S-C, Tsai J-H, Li Y., NCHC, TW

As the gate length of MOSFET devices shrinks down below 100 nm, the fluctuation of major devices parameter, namely, threshold voltage (VTH), subthreshold swing, drain current (ID) and subthreshold leakage current duo to influences of [...]

A Novel Method of Fabricating Optical Gratings Using the One Step DRIE Process on SOI Wafers

Cooper A.W., Docker P.T., Ward M.C., The University of Birmingham, UK

This paper describes a novel technique for manufacturing optical gratings by using the one step DRIE (Deep Reactive Ion Etching) process. Using the notching effect documented in previous work when working with silicon on insulator [...]

Pressure Sensor Elements Integrated with CMOS

Kiihamäki J., Vehmas T., Suni T., Häärä A., Ylimaula M., Ruohio J., VTT Information Technology, FI

We report the measurement and fabrication results of monolithically integrated capacitive pressure sensor elements. The device fabrication process is based on novel plug-up process, which enables monolithical integration of sensors and CMOS in a modular [...]

Silicon Nanostructures Patterned on SOI by AFM Lithography

Ionica I., Montès L., Ferraton S., Zimmermann J., Bouchiat V., Saminadayar L., IMEP-INPGrenoble, GF

The actual trends in microelectronics are the reduction of the dimensions and the search of new devices standing upon new phenomena as in the case of a Single Electron Transistor (SET) that is based on [...]

A Study of the Threshold Voltage Variations for Ultra-thin Body Double Gate SOI MOSFETs

Tang C-S, Lo S-C, Lee J.W., Tsai J-H, Li Y., Natl Nano Device Labs & Natl Chiao Tung Univ, TW

Double gate silicon on insulator (SOI) devices are more and more attractive for sub-50 nm ultra-large scaled integrated (ULSI) circuits manufacturing. The double gate SOI devices, owing to a difficulty of manufacturing uniformity, suffer fluctuations [...]

Predicting the SOI History Effect Using Compact Models

Na M-H, Watts J.S., Nowak E.J., Williams R.Q., Clark W.F., IBM Corporation, US

A simple and effective compact model methodology that predicts the history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter [...]

Gate Length Scaling Effects in ESD Protection Ultra-thin Body SOI Devices

Lee J.W., Li Y., Sze S.M., Natl Nano Device Labs & Natl Chiao Tung Univ, TW

In this paper we experimentaly explore the gate length scaling effects which related to the abrupt degation of electrostatic discharge (ESD) robustness for ultra-thin body silicon on insulator (SOI) devices and integrated circuits (ICs). It [...]

SOI Processing of a Ring Electrokinetic Chaotic Micromixer

Zhang Y.T., Chen H., Mezic I., Meinhart C.D., Petzold L., MacDonald N.C., university of california, santa barbara, US

Micromixing has been an active research area in the past decade due to the rapid expanding application of the lab-on-a-chip system in life science. Using the silicon bulk micromachining technology, a ring electroosmotic micromixer, which [...]

Single Transistor AND Gate

Chengalvala V., Zhang Y., Oklahoma State University, US

Double-gate SOI MOSFET structure opens the door for many novel devices by the coupling of the two gates. If the same voltage is applied to both gates, the depletion regions are equally partitioned. On the [...]

Process for Extremely Thin Silicon-on-Insulator Wafer

Usenko A.Y., Carr W.N., Chen B., Silicon Wafer Technologies, Inc., US

We observe hydrogen platelets buildup into single crystalline silicon caused by hydrogen plasma processing. The platelets are aligned along a layer of lattice defects formed in silicon before plasma processing. The buried defect layer is [...]