Double-gate SOI MOSFET structure opens the door for many novel devices by the coupling of the two gates. If the same voltage is applied to both gates, the depletion regions are equally partitioned. On the other hand, if the voltage is applied only to one gate, and keeping the other gate grounded (for NMOS), the two depletion regions are asymmetric. In these two situations, the threshold voltages are different. The SOI MOSFET can be designed in a way such that the double-gate threshold voltage is less than VDD and the single-gate threshold voltage is greater than VDD. If the two gates are connected with two logic inputs (A and B), the conducting condition of this gate is that both A and B are high. In this way, an AND pass-transistor logic gate is implemented with a single transistor. A simplified double-gate NMOS structure is investigated by numerical simulation. If the oxide thickness is 26 nm, the single-sided threshold voltage is 1.11V, and the double-sided threshold voltage 0.86 V, if the power supply voltage is 1V, the function of the single-transistor AND gate can be realized.
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 5 - 7
Industry sector: Sensors, MEMS, Electronics