A simple and effective compact model methodology that predicts the history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter during switching. These parameters are very challenging to measure accurately for sub-100nm devices, yet are very tightly correlated with the history effect. This methodology provides an effective means of adjusting history effects without significant alteration of the DC model. Furthermore this methodology enables construction of evaluation-level models in which DC device parametric, circuit performance and history goals exist but hardware meeting those goals is not yet available for model extraction.
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2
Published: March 7, 2004
Pages: 183 - 186
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling