double-gate – TechConnect Briefs

A Novel Dual-K Spacer Double Gate Junctionless Transistor for Digital Integrated Circuits

Patil G.C., Patil S.R., Patil G.C., Patil S.R., Borse H.S., Bhosale K.S., Jawake A.V., Aher S.R., JSPM’s Rajarshi Shahu College of Engineering, IN

Recently, junctionless transistors (JLT) have attracted the attention of researchers due to simple fabrication flow and reduced short channel effects. Further, due to better gate control double gate JLT (DGJLT) seems to be a promising [...]

Source/Drain Edge Modeling for DG MOSFET Compact Model

Nakagawa T., O’uchi S., Sekigawa T., Tsutsumi T., Hioki M., Koike H., AIST (National Institute of Advanced Industrial Science and Technology), JP

A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]

A Unified Charge-Based Model for SOI MOSFETs Valid from Intrinsic to Heavily Doped Channel

Zhang J., Zhang L., He J., Zhang J., Zhang L., Zhou X., Zhou Z., Zhou X., Zhou Z., Peking University, CN

A unified charge-based model for SOI MOSFETs is presented. The proposed model is valid and accurate from intrinsic to heavily doped channel with various structure parameter variations. The framework starts from one-dimension Poisson-Boltzmann’s equation. Based [...]

1/f Noise Model for Double-Gate FinFET Biased in Weak Inversion

Wei C.Q., Xiong Y.Z., Zhou X., Nanyang Technological University, SG

1/f noise model of long channel lightly-doped FinFET biased in weak inversion has been described using Hooge’s theory. From the drain current equation and the channel conductance expression, the total number of carriers under the [...]

An Analytical Solution to a Double-Gate MOSFET with Doped Body

Agarwal N., Bandhawakar G., Amity School of Engineering & Technology, Amity University, IN

ABSTRACT A CMOS scaling is approaching the limit imposed by gate oxide tunneling. Double gate MOSFET (DGMOSFET) with undoped body has become very attractive for scaling CMOS devices down to nanometer size. Device simulation predict [...]

Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices

Nakagawa T., Sekigawa T., Tsutsumi T., Liu Y., Hioki M., O’uchi S., Koike H., Electroinformatics Group, JP

We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two [...]

Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping

Hariharan V., Thakker R., Patil M.B., Vasi J., Rao V.R., IIT Bombay, IN

In this paper we present a completely closed-form inversion charge-based model for the drain current and conductance of a symmetric double-gate MOSFET based on the drift-diffusion transport mechanism, that takes into account vertical field mobility [...]

Keywords: double-gate