IBM – Page 2 – TechConnect Briefs

Impact of Gate-Induced-Drain-Leakage current modeling on circuit simulations in 45nm SOI technology and beyond

Wang H., Williams R., Wagner L., Johnson J., Hyde P., Springer S., IBM, US

Gate Induced Drain Leakage (GIDL) current is one of the most important leakage components in Silicon-on-Insulator (SOI) MOSFET devices. The effect of GIDL current reported before mainly focused on device characteristics in the OFF-state or [...]

Elements of Statistical SPICE Models

Lu N., Watts J., Springer S.K., IBM, US

We discuss several elements of statistical SPICE models and present our solutions. We present (i) a solution of automatically detecting Monte Carlo vs. skewed simulations, (ii) a method of modeling an arbitrarily given asymmetric or [...]

Modeling of Spatial Correlations in Process, Device, and Circuit Variations

Lu N., IBM, US

We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA approach, we give a very compact expression to [...]

Methodology and Design Kit Integration of a Broadband Compact Inductor Model

Groves R., Gordon E., IBM, US

A physics-based broadband inductor model is presented that accurately captures geometry scaling, process statistics, and temperature dependence. The model utilizes an accurate and physical skin effect formulation, with substantial improvements over previous methods, along with [...]

Optimal Skew Corners for Compact Models

Lu N., IBM, US

We present an innovative approach to generate an optimal skew corner of a compact device model (e.g., a Spice model) for a single performance target, and to generate a common/optimal skew corner of a compact [...]

Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types

Park J-E, Park S-J, Liang C-H, Assenmacher J., Watts J., Park J-E, Park S-J, Wachnik R., IBM, US

MOSFET device of similar design but different threshold voltage are often built on a single chip. It is important to be able to simulate with a compact model the variation of such devices including the [...]

Modeling MOSFET Process Variation using PSP

Watts J.S., Lee Y.M., Park J-E, IBM, US

The PSP model has been extensively evaluated for it’s abililty accurately match IV and CV characteristics MOSFETs measured on a single die. This enables accurate prediction of circuit behavior for circuits made of transistors which [...]

A Simple Yet Accurate Mismatch Model For Circuit Simulation

Jin Z., Lee Y.M., Watts J.S., Bonaccio A.R., Schroer G.J., Pai N.G., IBM, US

As technology scales, mismatch between a pair of transistors becomes a more and more critical issue for technology development and circuit designs. Scaling also increases the complexity of compact device modeling. Sophisticated models are usually [...]

Modeling Small MOSFETs using Ensemble Devices

Watts J.S., Pino R., Trombley H., IBM, US

This paper discribes methodogy to correctly model small area MOSFETs including paremeter extraction and centering using multiple parallel devices for accurate measurments. The method includes adjusting the measured data to recover true single finger behavior, [...]

Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices

Watts J., Lu N., Bittner C., Grundon S., Oppold J., IBM, US

In addition to the overall range of circuit characteristics expected from process variation the circuit designer needs to know how closely different circuit element will track one another. We describe a new methodology for modeling [...]