US – Page 449 – TechConnect Briefs

A Comparative Study of Double-Gate and Surrounding-Gate MOSFETs in Strong Inversion and Accumulation Using an Analytical Model

Chen Y., Luo J., University of California-Berkeley, US

An analytical model for the electric characteristics of ultrathin double-gate and surrounding-gate MOSFETs in strong inversion and accumulation is presented. The analytical solutions to the 1-D simplified Poisson's equation in both Cartesian and cylindrical coordinates [...]

Simulation of HgCdTe Double Layer Heterojunction Detector Devices

Hess G.T., Sanders T.J., Newsome G., Fischer T., Florida Institute of Technology, US

Mercury-Cadmium-Telluride (HgCdTe) diodes are used as detectors of long wavelength photons by interaction of the infrared radiation with the atomic lattice of the material, creating hole-electron pairs and subsequent photocurrents. Models for these physical phenomena [...]

Investigation of the Mechanism of Floating Node Assisted CMOS Latch-Up

Sim S-P., Guo P., Kordesch A., Chen W.F., Liu C-M., Yang C.Y., Lee K., Santa Clara University, US

A new phenomenon of floating node assisted CMOS latch-up is experimentally observed and investigated using TCAD simulation. Using test structures having parasitic bipolar transistors and an electrically floating N+ diffusion node located at various distances [...]

Determination of Low-Frequency Noise Spectrum in Ion-sensitive Field Effect Transistors (ISFET’s) Based on a Physical Model for Drift

Jamasb S., Collins S.D., Smith R.L., Conexant Systems, US

A physical model for drift in pH-sensitive ISFET's is employed to extract the inherent low-frequency noise power spectral density associated with these devices. The noise spectrum extracted from measured drift data demonstrates ideal 1/f noise [...]

A Model for Fully Depleted Double Gate SOI MOS Transistors Including Temperature Effects

Gharabagi R., St. Louis University, US

A model for a fully depleted double gate Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) Transistors is presented. Small geometry effects such carrier velocity saturation, mobility degradation, and channel length modulation are included. Both [...]

Substrate Current Simulations at Elevated Temperatures

Lyumkis E., Mickevicius R., Polsky B., Loechelt G., Zlotnicka A., Thoma R., Integrated Systems Engineering, Inc., US

We report results of hydrodynamic simulations and measurements of substrate currents in submicron MOSFET. Both simulations and measurements show anomalous dependence of the substrate current on lattice temperature, which is consistent with previously published experimental [...]

3-D Simulation and Modeling of Signal Isolation in RF/IF Circuits

Bharatan S., Welch P., To K.H., Thoma R., Huang M., Motorola, Digital DNA Laboratories, US

In this paper, we present a practical methodolgy for the 3-dimensional simulation of signal isolation structures along with comparison to measurements made on test structures. We also describe the extraction of a scalable compact model [...]

Spatial Modulation of the Dielectric Permittivity and its Effect on the Spectral Responsivity of Heterodimensional Photodetectors

Castro F., Nabet B., Motorola Laboratories, US

Spectral photocurrent measurements on AlGaAs/GaAs heterodimensional detectors show a peak near the absorption edge of GaAs under low incident power and at high biasing levels. Previous work has attributed similar results to the Franz-Keldysh spectral [...]

Numerical Simulation and Analytical Modeling of Strong-Inversion Gate Capacitance in Ultra-Short (30nm) MOSFETs

Sudhama C., Spulber O., McAndrew C., Thoma R., Motorola SPS, US

Bulk and novel MOSFET structures with gate-lengths in the 30nm regime are to become industry standards in ~2007. As devices are scaled down to these lengths, overlap- and fringe-capacitance between the gate and source/drain regions [...]

A Framework for Mask-Layout Synthesis Implementing a Level Set Method Simulator

Lee C.-Y., Antonsson E.K., California Institute of Technology, US

Recently, evolutionary methods have been developed to automate MEMS mask-layout synthesis [3]{[6]. These design synthesis methods are iterative searches in which each iteration consists of mask-layout modification, determination of etched shape via an arbitrary 3-D [...]