US – Page 415 – TechConnect Briefs

Compact Modeling for RF and Microwave Integrated Circuits

Niknejad A.M., Chan M., Hu C., Brodersen B., Xi J., He J., Emami S., Doan C., Cao Y., Su P., Wan H., Dunga M., Lin C.H., University of California at Berkeley, US

Compact modeling has been an integral part of the design of integrated circuits for digital and analog applications. The availability of scalable CMOS device models has enabled rapid simulation and design of present and future [...]

BJT Modeling with VBIC, Basics and V1.3 Updates

McAndrew C., Bettinger T., Lemaitre L., Tutt M., Motorola, US

This paper reviews the VBIC BJT model, and details updates in the version 1.3 release. VBICv1.3 includes explicit interaction with siulator global parameters gmin and pnjmaxi, explicit limiting of local temperature rise and exponential arguments [...]

A Physics-Based Compact Model for Nano-Scale DG and FD/SOI MOSFETs

Fossum J., Ge L., Chiang M-H, University of Florida, US

A process/physics-based compact model (UFDG) for double-gate (DG) MOSFETs is overviewed. The model, in essence, is a compact Poisson-Schrödinger solver, including accountings for short-channel effects, and is applicable to nano-scale fully depleted (FD) SOI MOSFETs [...]

An Advanced Surface-Potential-Plus MOSFET Model

He J., Xi X., Chan M., Niknejad A., Hu C., University of California at Berkeley, US

Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet approximation, uses the quasi-Fermi-potential to integrate drift and diffusion current and formulates an inversion charge equation that can be analytically solved for given terminal [...]

USIM Design Considerations

Bell A., Singhal K., Gummel H., Agere Systems, US

Compact models need to be carefully designed to predict circuit behavior efficiently, accurately and robustly. A variety of effects must work together and be consistently integrated into the model equations with redundancy. USIM is a [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]

Threshold Voltage Shifts in Narrow-Width SOI Devices Due to Quantum Mechanical Size-Quantization Effects

Ahmed S.S., Vasileska D., Arizona State University, US

We investigate the role of quantum-mechanical size-quantization effects in narrow-width SOI devices. In these structures, carriers experience a two dimensional confinement in a square quantum well at the semiconductor-oxide interface. This results not only in [...]

Quantum mechanical effects correction models for inversion charge and I-V characteristics of the MOSFET device

Abebe H., Cumberbatch E., MOSIS, US

A 1-dimensional analytic quantum mechanical effects correction formula for the MOSFET inversion charge and I-V characteristics are derived from the density gradient (DG) model using matched asymptotic expansion techniques. The primary theoretical framework for this [...]

Quantum and Kinetic Simulation Tools for Nano-scale Electronic Devices

Fedoseyev A., Kolobov V., Arslanbekov R., Przekwas A., Balandin A., CFD Research Corporation, US

The progress in LSI technologies has resulted in scaling down semiconductor devices to nano-scale dimensions where kinetic and quantum effects in the carrier transport become crucial for the device performance. The transistor counts on the [...]

A Quantum Waveguide Array Generator For Performing Fourier Transforms

Akis R., Ferry D.K., Arizona State University, US

Recently, quantum computing has gained attention as a possible means of greatly increasing the speed of certain calculations when compared with traditional, binary computing. A key part of many quantum computing algorithms is the performance [...]