The progress in LSI technologies has resulted in scaling down semiconductor devices to nano-scale dimensions where kinetic and quantum effects in the carrier transport become crucial for the device performance. The transistor counts on the high-end microprocessor is rushing toward the 400-million mark and the feature dimensions are shrinking toward the nanometer scale. As a result, the kinetic and quantum effects in the carrier transport and thermal conductivity in semiconductor nanostructures are beginning to attract significant attention. Designing an efficient simulation tool for nano-scale and quantum devices involves a trade-off between efficiency and accuracy. We have developed a novel simulation tool for nano-scale quantum devices based on deterministic solution of the classical Boltzmann equation with quantum corrections proposed in Ref . Using two-term spherical harmonic expansion in velocity space reduces the Boltzmann equation for electrons to a Fokker-Planck equation in a four-dimensional space (3 spatial and 1 energy dimensions). The Fokker-Planck equation is coupled to the Poisson and hole-continuity equations as described in Ref. . We describe the details of numerical implementation of the 4-dimensional Fokker-Planck solver using kinetic and total energy domains. The effect of quantum corrections on spatial distribution of carriers will be analyzed. This solver provides a substantially lower computational cost than the Monte Carlo method, and resolves all points in phase space with equal accuracy. We will present simulation results for an ultra-small 2D NMOSFET , compared well with experimental data. We work on software that will provide a practical simulation tool for nano-scale semiconductor devices. Two numerical methods are employed, the finite volume technique with time-splitting factorization of spatial and energy space transport, and a meshless multiquadric technique . References 1. H. Tsuchiya and T. Miyoshi, IEICE Trans. Electron E82-C, (1999) 880. 2. W. Liang, N. Goldsmann, I. Meyergoyz, P.J. Oldiges, IEEE Trans. Electron Devices, 44, (1997) 257. 3. D.A.Antoniadis et all. MIT Well-Tempered Bulk-Si NMOSFET Device, MIT, MS, 1999, http://www-mtl.mit.edu/Well/ 4. E.J. Kansa, Comput. Math. Applic., 19, No.8/9 (1990), 147-161.
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 214 - 217
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Modeling & Simulation of Microsystems