Papers – Page 5 – TechConnect Briefs

High-Voltage LDMOS Compact Modeling

Willemsen M.B., van Langevelde R., Klaassen D.B.M., Philips Research, NL

In compact modeling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is [...]

Effects of Scaling on Modeling of Analog RF MOS Devices

Liu Y., Cao S., Oh T.Y., Wu B., Tornblad O., Dutton R.W., Stanford University, US

This paper uses advanced TCAD tools—both IMF-based noise modeling and HB-based distortion modeling—to extract parameters of key importance in developing compact models. Additionally, the TCAD-based modeling provides insight into technology constraints that can potentially influence [...]

Modeling Small MOSFETs using Ensemble Devices

Watts J.S., Pino R., Trombley H., IBM, US

This paper discribes methodogy to correctly model small area MOSFETs including paremeter extraction and centering using multiple parallel devices for accurate measurments. The method includes adjusting the measured data to recover true single finger behavior, [...]

Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences

McAndrew C.C., Drennan P.G., Freescale Semiconductor, US

Partial correlations between parameters of different types of devices, such as effective channel lengthfor PMOS and NMOS devices, are often modeled and simulated statistically via correlation coefficients.However this is cumbersome and inefficient from a modeling [...]

On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body

Wong M., Shi X., Hong Kong University of Science and Technology, HK

Three general classes of solutions are needed to model an arbitrary double-gate (DG) metal-oxide-semiconductor (MOS) capacitor with arbitrary bias conditions. The “zero-field” (F0) and the “zero-potential” (P0) solution regimes are separated by the “zero-field and [...]

An Explicit Quasi-Static Charge-Based Compact Model for Symmetric DG MOSFET

Prégaldiny F., Krummenacher F., Sallese J.M., Diagne B., Lallement C., InESS, FR

This paper presents a closed-form compact model for the undoped double-gate (DG) MOSFET under symmetrical operation. This charge-based model aims at giving a comprehensive understanding of the device from the circuit design point of view. [...]

DC to RF Small-Signal Compact DG MOSFET model

Lázaro A., Moldovan O., Cerdeira A., Fjeldly T.A., Universitat rovira i Virgili (URV), ES

In this paper we present a complete compact model for doped DG MOSFETs which includes explicit expressions of the channel current and of all small- and large-signal parameters. The model is based on a unified [...]

Recent Upgrades and Applications of UFDG

Fossum J.G., Trivedi V.P., Chowdhury M.M., Kim S-H, Zhang W., University of Florida, US

Recent upgrades of UFDG, a process/physics-based compact model for nonclassical MOSFETs having ultra-thin Si bodies (UTB), are overviewed, and several recent applications of the model are presented, exemplifying the potential benefits of FinFETs in nanoscale [...]

Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques

Fjeldly T.A., Kolberg S., Norwegian University of Science and Technology, NO

In nanoscale double gate MOSFETs, the dependence on the bias voltages of the 2D electron barrier topology in the conducting channel is all-important for the operation of the device. We consider a DG MOSFET with [...]

A Charge-Based Compact Model of Double Gate MOSFET

Roy A.S., Enz C.C., Sallese J.M., CSEM, CH

To date, a simple physical compact model is still lacking even for the ‘classical’ asymmetric DG MOST because of it’s relatively complex electrostatics. Ref [1] has presented an exact solution for symmetric DG MOST but [...]