Papers – TechConnect Briefs

Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors

Galup-Montoro C., Paim V.C., Schneider M.C., Federal University of Santa Catarina, BR

In this communication we present a charge-based formulation for the thermal noise in short-channel MOS transistors. We arrive at a closed expression for the channel noise including velocity saturation for all the operating regions of [...]

A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram

Burghartz J.N., Mijalkovic S., Wu H.C., Delft University of Technology, NL

A unified parameters extraction procedure for temperature and geometry scalable bipolar transistor model Mextram has been demonstrated using an example of high-speed SiGe HBT technology. The essential feature of the proposed methodology is a direct [...]

Interrelations between Threshold Voltage Definitions and Extraction Methods

Cunha A.I.A., Galup-Montoro C., Machado M.B., Schneider M.C., Federal University of Santa Catarina, BR

This paper presents a brief discussion on the main MOSFET threshold voltage definitions available in the literature as well as on associated extraction methodologies. In order to compare these definitions and methodologies, we take advantage [...]

Static Analog Design Methodology

Guigues F., Kussener E., Rudolff F., L2MP UMR 6137 CNRS - ISEN-Toulon, FR

When strong constraints of supply voltage (< 1V ) and bias current (< 100nA) are required, the only way to meet design’sspecifications without using huge silicon area consists on decreasing transistor’s inversion level and therefore [...]

A transient circuit model for a phase change memory element

Huizing H.G.A., Lankhorst M.H.R., Paasschens J.C.J., Tio Castro D., Philips, NL

A transient lumped element model for a phase change memory (PCM) cell is developed for use in a circuit simulator. Unlike existing models, this model calculates threshold voltage and off-state resistance drift as found in [...]

Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology

Chidambarrao D., McCullen J.H., Mitchell T.G., Narasimha S., Onsongo D., Williams R.Q., IBM Corporation, US

This work presents a novel methodology for a physically-based, layout-dependent nitride liner stress model that works with readily-available compact models. The methodology includes a data-calibrated, semi-empricial model and is tightly-coupled to circuit netlist extraction for [...]

Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs

Kumar M.J., Nawal S., Venkataraman V., Indian Institute of Technology, IN

A simplae compact model for the threshold voltage of Strained Si/SiGe MOSFET is reported for the first time. This model accurately predicts the effects of Ge content and other device parameters on threshold voltage. The [...]

A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors

Chen J., Agere Systems, US

Silicon nanowire transistors (SNWT) are being extensively explored as a successor to CMOS. Silicon nanowires with a diameter as small as 2nm and having high carrier mobility have been achieved. Such developments shed light on [...]

A Compact Model of Ballistic CNFET for Circuit Simulation

Fujita S., Lee T., Okajima M., Paul B.C., Toshiba America Research Inc., US

As silicon technology is approaching to its limit, Carbon nanotube FETs (CNFET) are shown to have potential of taking this place in the post silicon era. Consequently, interests have grown to predict the performance of [...]

Enhanced Junction Capacitance Modeling

Anderson F.G., Lavoie M.A., Rassel R.M., IBM Microelectronics, US

The current standard diode junction capacitance models do not yield high quality models for hyperabrupt junction varactors that are constructed from several implants. We describe a new enhancement that employs the actual (exponential) doping profiles [...]