Papers – Page 5 – TechConnect Briefs

Cellular Automata Studies of Vertical MOSFETs

Saraniti M., Wigger S., Zandler G., Formicone G., Goodnick S.M., Arizona State University, US

This paper presents an overview of the cellular automata (CA) method for semiconductor device simulation. The main advantages of the CA method over the Monte Carlo (MC) approach are presented, and limitations of its modeling [...]

A Physics-Based Characterized Model for an Ultrafast Planar Rectifier

Hossain Z., Fragale W., Simpson W., Dashney G., Motorola, Inc., US

This paper presents a characterized nodel for an ultrafast-recovery (UFR) rectifier based on the manufacturing processes and device structural geometry. The accuray of the developed model depends upon the proper selection of physical models and [...]

Hierarchical Approach to Simulation in a Vertical System for the TriCore Microcontroller

Salzmann C., Chesters E., Coelho P., Fu Y-C, Madala J., Reddy M., Wang F., Siemens Microelectronics, Inc., US

This paper describes a hiercihical functional verification system for a core-based system design which minimizes complexity in testbenches while maximizing flexibility in terms of number of clocks and system interfaces and reducing time-to-market. The verification [...]

Simulations of a New CMOS Compatible Method to Enhance the Breakdown Voltage of Highly-Doped Shallow PN Junctions

Pauchard A., Besse P.A., Popovic R.S., EPFL, CH

Avalanche breakdown often limits the working range of planar junction diodes in electronic circuits and in sensors. We present two-dimensional device simulation results (using MEDICI) of a novel CMOS compatible structure. It combines a floating [...]

Concurrent Process, Device and Integrated Circuit Development by Predictive Engineering for Smart Power Technologies

Bafleur M., Dinh T., Park H., Thoma R., Zirkle T., Wild A., LAAS/CNRS, FR

Predictive TCAD has been shown to be a powerful tool for the development of low voltage CMOS and VLSI memory technology development [1], [2] in which the main features of advanced p-channel and n-channel MOS [...]

The Influence of Space Quantization Effect on the Threshold Voltage, Inversion Layer and Total Gate Capacitance in Scaled Si-MOSFETs

Vasileska D., Ferry D.K., Arizona State University, US

We investigate the influence of poly-gate depletion on the inversion layer capacitance CinV, total gate capacitance CtOt and threshold voltage VT in scaled Si MOSFETs using both semiclassical (SC) and quantum-mechanical (QM) description of the [...]

FELLINI-A CAD Tool for the Design of Microsystems

Lang M., Glesner M., Darmstadt University of Technology, DE

This paper reports of the CAD-tool FELLINI, which supports the design of microsysfems on the lower levels of abstraction. FELLINI provides a bidirectional interface between the structural and the layout level. A Layout-to-FEM converter as [...]

DOPDEES/PMM: A System for Portable Model Description

Gencer A.H., Dunham S.T., Boston University, US

We have developed a multi-purpose partial differential equation solver, DOPDEES, which is capable of solving initial value problems in one spatial dimension using a finite differences method. The system of partial fferential equations is specified [...]

Multi-Mode Sensitive Layout Synthesis of Microresonators

Iyer S., Mukherjee T., Fedder G.K., Carnegie Mellon University, US

Microresonator layouts are synthesized such that their preferred mode of oscillation is well-separated from the higher order in-plane and out-of-plane modes. Building on our previous work, we have incorporated models for four out-of-plane modes. All [...]

An Environment for MEMS Design and Verification

Bart S.F., Swart N.R., Mariappan M., Zaman M.H., Gilbert J.R., Microcosm Technologies, Inc., US

A comprehensive CAD software environment is presented for MEMS/MST design. It includes MEMS mechanical schematic entry, parameterized cell layout generation, automatic lumped parameter macro-model generation, and LVS style error checking. These tools allow for flexible [...]