WCM – Compact Modeling – Page 7

Analytical Modelling of Ballistic and Quasi-Ballistic Nanowires:Validation and Application to CMOS Architecture

Martinie S., Munteanu D., Le Carval G., Jaud M-A, Autran J-L, CEA/LETI/MINATEC, FR

We present here an unified analytic model for ballistic and quasi-ballistic Silicon Nanowire (SNW represented in figure 1). Starting from the classical flux method and using the Lundstrom/Natori approaches [1-2], we enhanced them by taking [...]

Design study of CNT transistors layouts for high frequency analog circuits

Claus M., Technische Universität Dresden, DE

CNTFET technology is examined for high speed analog circuits. Design guidelines are deduced based on a realistic extrinsic circuit model. Moreover, numerical device simulations are used to derive specifications for CNTFET compact models suitable for [...]

Effective Width Modeling for Body-Contacted Devices in Silicon-On-Insulator Technology

Khandelwal S., Tamilmani E., Shanbhag K., Watts J., IBM SRDC Bangalore, IN

Body-Contacted (BC) devices are extensively used in silicon-on-insulator analog circuits to avoid kink effect. This effect is not desirable as it changes gain of device suddenly. But to make body-contact special layout schemes are used. [...]

Dynamic Charge Sharing modeling for surface potential based models

Quenette V., Rideau D., Clerc R., Tavernier C., Jaouen H., ST Microelectronics, FR

Technology tuning by design means have been recently pointed out. Particularly, the possibility of back bias polarization (VB) to tune the threshold voltage (VT) has been commonly adopted in advanced devices. As a consequence the [...]

Embedded non–volatile memory study with surface potential based model

Garetto D., Zaka A., Quenette V., Rideau D., Dornel E., Clark W.F., Minondo M., Tavernier C., Rafhay Q., Clerc R., Schmid A., Leblebici Y., Jaouen H., STMicroelectronics, FR

Coupling coefficients calculation is known to be a critical issue in Non-Volatile Memory cell compact modelling. To this purpose, the accuracy of the capacitive network method can be significantly improved using the charge balance method, [...]

HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization

Sadachika N., Kusu S., Ishimura K., Murakami T., Kajiwara T., Hayashi T., Nishikawa Y., Yoshida T., Miura-Mattausch M., Hiroshima University, JP

SOI-MOSFETs are considered to be suitable for high performance as well as low power applications and its developments are tend to go toward the thinner SOI films to enhance the device characteristics. Thus compact models [...]

Analytic MOSFET Surface Potential Model with Inclusion of Poly-Gate Accumulation, Depletion, and Inversion Effects

Song Y., He J., Zhang J., Zhang L.N., Zhang J., Zhang L.N., Peking University, CN

An analytic MOSFET surface potential model with inclusion of the poly-gate accumulation, depletion, and inversion effects is derived from the basic MOS device physics and its solution result is also discussed in this paper. By [...]

Interface Traps in Surface-Potential-Based MOSFET Models

Chen Z., Zhou X., See G.H., Zhu G., Zhu Z., Zhu G., Zhu Z., Nanyang Technological University, SG

Surface or interface properties along the surface channel region have great influences on the MOSFET characteristics. The interface-trap density increases during the repeated program-erase cycling of non-volatile floating-gate and SONOS memory transistors. Thus, the compact [...]

What is a Transistor?

Sah C., Jie B., University of Florida, US

After 75 years of learning vacuum tube and solid state electronics in three human generations, we now come to the end of the complete understanding of what is a transistor. It is far beyond, eight [...]

Topic: WCM - Compact Modeling