Surface or interface properties along the surface channel region have great influences on the MOSFET characteristics. The interface-trap density increases during the repeated program-erase cycling of non-volatile floating-gate and SONOS memory transistors. Thus, the compact modeling community faces great challenges to model the interface-trap effect, which is an important step towards modeling device reliability. In this work, the unified regional surface potential (URSP) approach is extended to explore the effect of interface traps at the SiO2/Si interface on the surface-potential and gate-capacitance lineshapes in bulk MOSFETs. Due to the trapped charges alone surface channel region, the interface traps significantly distort the surface-potential and gate-capacitance curves. The result shows that the explicit URSP model has powerful capability to characterize interface-trap properties without major loss of accuracy.
Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2009: Biofuels, Renewable Energy, Coatings, Fluidics and Compact Modeling
Published: May 3, 2009
Pages: 542 - 545
Industry sector: Sensors, MEMS, Electronics
Topic: WCM - Compact Modeling