Sensors, MEMS, Electronics – Page 150

Neural Computational Approach for FinFET Modeling and Nano-Circuit Simulation

Alam M.S., Kranti A., Armstrong G.A., Z. H. College of Engineering & Technology, IN

FinFETs are very promising for low power, low voltage portable applications. For nano-circuit simulation, a suitable FinFET model is required. A behavioural model based on a neural network has been developed in this work and [...]

Compact Models for Double Gate MOSFET with Quantum Mechanical Effects using Lambert Function

Abebe H., Morris H., Cumberbatch E., Tyree V., University of Southern California, ISI, US

This paper is a continuation of the work we presented in the 2006 IEEE UGIM Proceedings. Iterative compact device models with quantum mechanical effects for a Double Gate (DG) MOSFET are presented using the Lambert [...]

Parameter Extraction for Advanced MOSFET Model using Particle Swarm Optimization

Thakker R.A., Patil M.B., Anil K.G., Indian Institute of Technology, IN

In the sub 100-nm regime, MOSFET parameter extraction has become a challenging task. Commonly used gradient based methods have many difficulties such as good initial guess requirement, singularities in objective functions, etc. Genetic Algorithm (GA), [...]

An Improved Impact Ionization Model for SOI Circuit Simulation

Xi X., Li F., Liu W., Tudor B., Wang P., Wang W., Liu W., Lee F., Wang P., Wang W., Subba N., Goo J-S, Synopsys, Inc., US

The impact ionization (II) model accuracy issue in industry standard SOI MOSFET is discussed in the paper. Based on Medici 2D simulation study, an improved impact ionization model is proposed which can capture the voltage [...]

Analytical Modelling and Performance Analysis of Double-Gate MOSFET-based Circuit Including Ballistic/quasi-ballistic Effects

Martinie S., CEA/LETI/MINATEC, FR

As the MOSFET continues to shrink rapidly, emerging physical phenomena, such as ballistic transport, have to be considered in the modelling and simulation of ultra-scaled devices. Future Double-Gate MOSFETs, designed with channel lengths in the [...]

Process Aware Compact Model Parameter Extraction for 45 nm Process

Karmarkar A.P., Dasarapu V.K., Saha A.R., Braun G., Krishnamurthy S., Lin X-W, Synopsys (India) Pvt. Ltd., IN

The current industry trends call for smaller devices and decreasing feature sizes with each technology node. The process variability has a significant impact on the device characteristics for deep sub-micron technologies because of the smaller [...]

Effective Drive Current in CMOS Inverters for Sub-45nm Technologies

Hu J., Park J-E, Freeman G., Wong H.S.P., Stanford University, US

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average [...]

Modeling of gain in advanced CMOS technologies

Spessot A., Gattel F., Fantini P., Marmiroli A., STMicroelectronics, IT

The impressive downscaling of CMOS technology and its more and more massive introduction in System-on-chip (SoC) oriented applications require comprehensive modeling approach able to describe such different world (digital and analog) starting from a single [...]

Model Implementation for Accurate Variation Estimation of Analog Parameters in Advanced SOI Technologies

Suryagandh S., Subba N., Wason V., Chiney P., Wu Z-Y, Chen B.Q., Krishnan S., Rathor M., Icel A., Advanced Micro Devices, US

Analog design uses transistors with longer channel length for high performance. gm, Rout and intrinsic gain form the matrix to gauge this performance. It is critical to design these circuits for manufacturing variability. This work [...]

Modeling of Spatial Correlations in Process, Device, and Circuit Variations

Lu N., IBM, US

We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA approach, we give a very compact expression to [...]