SPICE – Page 2 – TechConnect Briefs

On Idlow with Emphasis on Speculative SPICE Modeling

Chen Q., Wu Z-Y, Icel A.B., Goo J-S, Krishnan S., Thuruthiyil C., Subba N., Suryagandh S., An J.X., Ly T., Radwin M., Yonemura J., Assad F., Advanced Micro Devices, US

An empirical correlation model of Idlow, the MOSFET drain current measured at Vgs=Vdd/2 and Vds=Vdd, where Vdd is the supply voltage, is proposed based on the alpha-power law model. It enables a comprehensive analysis of [...]

BJT Modeling with VBIC, Basics and V1.3 Updates

McAndrew C., Bettinger T., Lemaitre L., Tutt M., Motorola, US

This paper reviews the VBIC BJT model, and details updates in the version 1.3 release. VBICv1.3 includes explicit interaction with siulator global parameters gmin and pnjmaxi, explicit limiting of local temperature rise and exponential arguments [...]

A Framework for Generic Physics Based Double-Gate MOSFET Modeling

Chan M., Taur Y., Lin C.H., He J., Niknejad A., Hu C., Hong Kong University of Science & Technology, HK

This paper presents a framework to develop a generic and physical Double-Gate MOSFET model. Due to limited available physical data and existence of a large variety of device structures, flexibility to assemble model modules to [...]

Quasi-2D Compact Modeling for Double-Gate MOSFET

Chan M., Man T.Y., He J., Xi X., Lin C.H., Lin X., Lin C.H., Lin X., Ko P.K., Niknejad A.M., Hu C., Hong Kong University of Science and Technology, HK

This paper presents an approach to model the characteristics of undoped Double-Gate MOSFETs without relying on the charge-sheet approximation. Due to the extremely thin silicon film used, the inversion charge thickness becomes comparable to the [...]

How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

The downscaling of devices causes the unpredictability of analog circuit yield. Transistor mismatch is one of the obstacles to achieving high yield. Analog circuit designers usually run Monte Carlo mismatch models to predict the functionality [...]

SPICE Modeling of Multiple Correlated Electrical Effects of Dopant Fluctuations

Lee Y.M., Watts J., Grundon S., Cook D., Howard J., IBM Semiconductor Research and Developement Center, US

We proposed a new methodology capable of accurately modeling the partial correlations and geometric dependency in the local random fluctuations of various electrical parameters. This method incorporates principal factor analysis (PFA) into the conventional SPICE-based [...]

MOSFET Analytical Inversion Charge Model with Quantum Effects using a Triangular Potential Well Approximation

Abebe H., Cumberbatch E.C., Tyree V., Morris H.C., USC/ISI MOSIS, US

The eigenfunctions from solutions of the Schrödinger equation for a triangular potential well are the Airy functions. The triangular potential approximation has been shown to be a good approximation for the charge density when the [...]

Analytical Surface Potential Model with Polysilicon Gate Depletion Effect for NMOS

Cumberbatch E., Abebe H., Morris H., Tyree V., USC/ISI MOSIS, US

Different modeling approaches for the sub-100nm MOSFET are discussed in [1] and the surface potential description model is reported to be promising, [1, 2]. Surface potential changes impact gate capacitance and current-voltage (I-V) characteristics of [...]

Quasi-2D Compact Modeling for Double-Gate MOSFET

Chan M., Man T.Y., He J., Xi X., Lin C.H., Lin X., Lin C.H., Lin X., Ko P.K., Niknejad A.M., Hu C., Hong Kong University of Science and Technology, HK

This paper presents an approach to model the characteristics of undoped Double-Gate MOSFETs without relying on the charge-sheet approximation. Due to the extremely thin silicon film used, the inversion charge thickness becomes comparable to the [...]

An Improved Single-Electron-Transistor Model for SPICE Application

Wu Y-L, Lin S-T, National Chi-Nan University, TW

Single electron transistors (SETs) have drawn much attention of researchers and scientists because they are considered candidate as one of the elements for future low power, high-density memories and logic circuits. Instead of using Monte [...]