MOSFET – Page 2 – TechConnect Briefs

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Zhou X., Zhu G.J., Srikanth M.K., Lin S-H, Chen Z.H., Zhang J.B., Wei C.Q., Yan Y.F., Selvakumar R., Nanyang Technological University, SG

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The [...]

Source/Drain Edge Modeling for DG MOSFET Compact Model

Nakagawa T., O’uchi S., Sekigawa T., Tsutsumi T., Hioki M., Koike H., AIST (National Institute of Advanced Industrial Science and Technology), JP

A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]

Electrostatic Potential Compact Model for Symmetric and Asymmetric Lightly Doped DG-MOSFET Devices

Abebe H., Cumberbatch E., Uno S., Tyree V., USC/ISI, US

The analytical symmetric and asymmetric lightly doped DG-MOSFET device electrostatic potential compact model presented here improves the compact model accuracy without any iteration. The model is developed using the Lambert Function and a 2-dimensional (2-D) [...]

Impact of Gate-Induced-Drain-Leakage current modeling on circuit simulations in 45nm SOI technology and beyond

Wang H., Williams R., Wagner L., Johnson J., Hyde P., Springer S., IBM, US

Gate Induced Drain Leakage (GIDL) current is one of the most important leakage components in Silicon-on-Insulator (SOI) MOSFET devices. The effect of GIDL current reported before mainly focused on device characteristics in the OFF-state or [...]

An SOA Aware MOSFET Model for Highly Integrated, Analog Mixed-Signal Design Environments

Hall J., Luo Z., Xiao Y., Young A., Connerney D., Fairchild Semiconductor, US

Circuit simulations involving power devices often require additional checks comparing with generic low power applications. The burden lies with the individual designers to ensure that the power transistors are operating well within the Safe Operating [...]

SPICE BSIM3 Model Parameters Extraction and Optimization for Low Temperature Application

Abebe H., Tyree V., Cockerham N.S., USC/ISI MOSIS, US

The SPICE BSIM3v3.1 model parameters extraction and optimization strategy that we present here is applicable for a half micron technology and circuits operating at temperature ranging from -191 to 125 0C. The room temperature extraction [...]

1/f Noise Modeling at Low Temperature with the EKV3 Compact Model

Martin P., Ghibaudo G., CEA/LETI/MINATEC, FR

Advanced compact models are mandatory for simulation of mixed analog-digital circuits working at low temperature (77-200 K). In this work, the 1/f noise model introduced in the EKV3 model is evaluated. This evaluation is performed [...]

RF Modeling of 45nm Low-Power CMOS Technology

Wang J., Li H., Pan L.H., Gogineni U., Groves R., Jagannathan B., Na M-H, Tonti W., Wachnik R., IBM Semiconductor Research and Development Center, US

As CMOS has grown to be one of the principle technologies for RF IC design, accurate modeling of MOSFETs at high frequencies becomes increasingly important. In this paper, we present an advanced RF modeling work [...]

A Scalable POWER MOSFET Model with an Integrated Body-Diode Including Reverse Recovery

Luo Z., Hall J., Xiao Y., Young A., Carroll R., Connerney D., Fairchild Semiconductor, US

Traditional high-voltage MOSFET models include parasitic source-bulk and drain-bulk diode models. However, these models are simplified diode models and lack some of the more detailed aspects of p-n junctions diodes such as breakdown voltage, advanced [...]

Analytic MOSFET Surface Potential Model with Inclusion of Poly-Gate Accumulation, Depletion, and Inversion Effects

Song Y., He J., Zhang J., Zhang L.N., Zhang J., Zhang L.N., Peking University, CN

An analytic MOSFET surface potential model with inclusion of the poly-gate accumulation, depletion, and inversion effects is derived from the basic MOS device physics and its solution result is also discussed in this paper. By [...]