MOS – TechConnect Briefs

Metal-Oxide-Semiconductor Structures with Two and Three-Region Gate Dielectric Containing Silicon Nanocrystals: Structural, Infrared and Electrical Properties

Mateos D., Arias A., Nedev N., Curiel M., Dzhurkov V., Manolov E., Nesheva D., Contreras O., Valdez B., Bineva I., Raymond O., Siqueiros J.M., Autonomous University of Baja California, MX

MOS structures with two and three-region gate dielectrics containing Si nanocrystals are prepared and characterized by TEM, IR spectroscopy and electrical measurements. c Si/SiO2 containing Si NCs/SiO2/Al structures were obtained by high temperature annealing of [...]

Investigation of Metal Nano Layer Formation by the Tunneling Current through the Thin Oxide Film in the Electrolyte–Oxide–Silicon System

Lee S-H., Cheon J-H, Choi S., Choi Y., Choi S., Choi Y., Park Y.J., Seoul National University, KR

In the researches on Electrolyte–Oxide–Silicon (EOS) system, tunneling current through the gate insulator has been considered as an undesirable factor causing reliability issues such as gate insulator degradation and interface state generation. In this work, [...]

Ab initio calculation of tunneling current through ultra-thin SiO2 gate dielectric of MOS Structure, including the influence of oxygen vacancies on the tunneling current

Nadimi E., Janisch R., Radehaus C., TU Chemnitz, DE

We used a first-principle atomistic scale method, based on density functional theory and non-equilibrium Green’s function to study the electron tunneling current through ultra thin silicon oxide films. The Si/SiO2 model interface has been constructed [...]

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models

Zhou Y., Connerney D., Carroll R., Luk T., Fairchild Semiconductor, US

A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a [...]

Influence of Si Nanocrystal Distribution on Electrical Characteristics of MOS Structures

Liu Y., Chen T.P., Ng C.Y., Ding L., Nanyang Technological University, SG

In this work, Si nanocrystals with different distributions were embedded in the gate oxide with ion implantation technique. C-V and time-domain capacitance measurements were conducted to study the electrical characteristics of MOS structures. It is [...]

A Nano-Transistor with a Cavity

Ravariu C., Ravariu F., Rusu A., Profirescu M., Ravariu C., Ravariu F., Politehnica University of Bucharest, RO

A SOI nanotransistor with a cavity was simulated. The global current is a superposition of a tunnel current through the cavity and an inversion current at the film bottom. The tunnel source-drain current prevails in [...]

Mismatch Improvement with XMOS Structure

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

MOS transistor has been continuously scaled down to improve the device performance. Smaller MOS transistors have higher transconductance (gm) and low capacitance, so the ratio gm/C is improved by shrinking. Shorter gate length provides higher [...]

Substrate Current Simulations at Elevated Temperatures

Lyumkis E., Mickevicius R., Polsky B., Loechelt G., Zlotnicka A., Thoma R., Integrated Systems Engineering, Inc., US

We report results of hydrodynamic simulations and measurements of substrate currents in submicron MOSFET. Both simulations and measurements show anomalous dependence of the substrate current on lattice temperature, which is consistent with previously published experimental [...]