interface traps – TechConnect Briefs

Analytical Drain Current Model for Damaged Gate All Around (GAA) MOSFET Including Quantum and Velocity Overshoot Effects

Gautam R., Saxena M., Gupta M., Gupta R.S., Gupta M., Gupta R.S., University of Delhi, South Campus, IN

The Cylindrical Gate All Around (GAA) Nanowire MOSFET exhibits strong drive currents and reduced short channel effects due to enhanced gate control and high surface quality of NW channels [1]. Apart from short channel immunity, [...]

Interface Traps in Surface-Potential-Based MOSFET Models

Chen Z., Zhou X., See G.H., Zhu G., Zhu Z., Zhu G., Zhu Z., Nanyang Technological University, SG

Surface or interface properties along the surface channel region have great influences on the MOSFET characteristics. The interface-trap density increases during the repeated program-erase cycling of non-volatile floating-gate and SONOS memory transistors. Thus, the compact [...]

Interface-trap Charges on Recombination DC Current-Voltage Characteristics in MOS transistors

Chen Z., Jie B.B., Sah C-T, Nanyang Technological University, SG

The interface traps and trapped charges along the surface channel region are generated during transistor stress or operation and primarily responsible for the changes of device properties. The threshold voltage is varied by the generation [...]

High Conentration of Interface Traps in MOS Transistor Modeling

Chen Z., Jie B.B., Sah C-T, Xiamen University, CN

Modifications of the MOS capacitor and transistor characteristics by the presence of a high concentration of interface traps are described. Change or distortion of the gate/base voltage dependent characteristics are presented, such as the gate [...]

A History of Electronic Traps on Silicon Surfaces and Interfaces

Sah C-T, Jie B.B., Chen Z., University of Florida, US

A review of the electronic or electron and hole traps on silicon surfaces and interfaces is given. They are increasingly affecting the electrical signal properties of silicon diodes and transistors as the technologies for digital, [...]

Mobility of Electrons in Rectangular Si Nanowires

Ramayya E., Vasileska D., Goodnick S.M., Knezevic I., Arizona State University, US

We investigate two issues in this paper. First, we examine the role of interface-traps on the device drain current in an SOI nanowire MOSFET. Afterwords, we investigate the role of the interface-roughness on the low-field [...]

Modelling of the “Gated-Diode” Configuration in Bulk MOSFET’s

Yip A., Yeow Y.T., Samudra G.S., Ling C.H., TECH Semiconductor, SG

A study of the “gated-diode” configuration in MOSFET’s for characterising hot-carrier degradation by employing 2-D simulations is presented in this paper. We use both process and device simulations to understand operational sensitivity of this technique. [...]