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HomeAuthorsWatts J.

Authors: Watts J.

A Fully Automated Method to Create Monte-Carlo MOSFET Model Libraries for Statistical Circuit Simulations

Wang J., Trombley H., Watts J., Randall M., Wachnik R., IBM Semiconductor Research and Development Center, US
As the MOSFET continues to shrink, device-to-device variations become increasingly important. Therefore, it is critical to develop accurate, Monte-Carlo (MC) models that capture various device variations to allow statistical circuit simulations. To model the global [...]

Elements of Statistical SPICE Models

Lu N., Watts J., Springer S.K., IBM, US
We discuss several elements of statistical SPICE models and present our solutions. We present (i) a solution of automatically detecting Monte Carlo vs. skewed simulations, (ii) a method of modeling an arbitrarily given asymmetric or [...]

Effective Width Modeling for Body-Contacted Devices in Silicon-On-Insulator Technology

Khandelwal S., Tamilmani E., Shanbhag K., Watts J., IBM SRDC Bangalore, IN
Body-Contacted (BC) devices are extensively used in silicon-on-insulator analog circuits to avoid kink effect. This effect is not desirable as it changes gain of device suddenly. But to make body-contact special layout schemes are used. [...]

Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types

Park J-E, Park S-J, Liang C-H, Assenmacher J., Watts J., Park J-E, Park S-J, Wachnik R., IBM, US
MOSFET device of similar design but different threshold voltage are often built on a single chip. It is important to be able to simulate with a compact model the variation of such devices including the [...]

SPICE Modeling of Multiple Correlated Electrical Effects of Dopant Fluctuations

Lee Y.M., Watts J., Grundon S., Cook D., Howard J., IBM Semiconductor Research and Developement Center, US
We proposed a new methodology capable of accurately modeling the partial correlations and geometric dependency in the local random fluctuations of various electrical parameters. This method incorporates principal factor analysis (PFA) into the conventional SPICE-based [...]

Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices

Watts J., Lu N., Bittner C., Grundon S., Oppold J., IBM, US
In addition to the overall range of circuit characteristics expected from process variation the circuit designer needs to know how closely different circuit element will track one another. We describe a new methodology for modeling [...]

Advanced Compact Models for MOSFETs

Watts J., McAndrew C., Enz C., Galup-Montoro C., Gildenblat G., Hu C., van Langevelde R., Miura-Mattausch M., Rios R., Sah C-T, Joint Paper, US
The combination of decreasing MOSFET dimensions and increasing use of MOSFETs for analog and RF application has created the need for advanced compact models for MOSFET circuit design. The first generation of MOSFET models rely [...]

A Compact Model Methodology for Device Design Uncertainty

Williams R., Watts J., Na M-H, Bernstein K., Internatoinal Business Machines Corporation, US
Todays ULSI chip and transistor technologies have a high degree of concurrency due to the complexity of new, advanced high performance features. This creates challenges for circuit designer who must account for the evolution of [...]

How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics

Watts J., IBM Microelectronics, US
An important application for partially depleted SOI is high performance microprocessors and other logic chips. In order to deliver market leading performance it is necessary for transistor design and circuit design to be done concurrently. [...]

Extraction of Compact Model Parameters for ULSI MOSFETs Using a Genetic Algorithm

Watts J., Bittner C., Heaberlin D., Hoffman J., IBM Microelectronics Division, US
Extracting an optimal set of parameter values for an FET device model is a complex problem. The final model must not only describe the performance of a set of hardware to an acceptable level of [...]

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