Papers – Page 4 – TechConnect Briefs

An Optimization Method of Deep Submicron SOI Compact Model Parameter Extraction

Mahotin Y., Mickevicius R., Synopsys, Inc., US

As SOI rapidly advances to the vanguard of ULSI technology, compact model parameter extraction for SOI still relies on indirect methods. Floating body (FB) device parameter extraction is currently based on body contact (BC) devices. [...]

HiSIM-1.2: The Effective Gate Length Validation with the Capacitance Data

Iino Y., Silvaco Japan, JP

HiSIM-1.2 model parameter extraction and the resulted fit for the current voltage characteristics were reported at WCM-2004 (Boston, MA, 2004). The measurement curves were reproduced well. However, the Cgc (the gate to the shorted source/drain) [...]

Airgap and Line Slope Modeling for Interconnect

Badrieh F., Puchner H., Cypress Semiconductor, US

We have devised a generic methodology for characterizing airgaps and line slope and including those features in interconnect modeling. The method is silicon-based and can be used to accurately model the impact on capacitance. Our [...]

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models

Zhou Y., Connerney D., Carroll R., Luk T., Fairchild Semiconductor, US

A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a [...]

How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

The downscaling of devices causes the unpredictability of analog circuit yield. Transistor mismatch is one of the obstacles to achieving high yield. Analog circuit designers usually run Monte Carlo mismatch models to predict the functionality [...]

A Compact I-V Model for FinFETs Comprising Multi-Dimensional Electrostatics and Quantum Mechanical Effects

Zhang D., Yu Z., Tian L., Tsinghua University, CN

A compact I-V model for FinFET using ballistic transport with 1D electron gas is presented. The 2D electrostatics and 2D quantum mechanical (QM) effects at the cross-section are fully taken into account, which ensures the [...]

Device Parameter Extraction from Fabricated Double-Gate MOSFETs

Tsutsumi T., Liu Y., Nakagawa T., Sekigawa T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology (AIST), JP

Accurate spice simulation needs parameter extraction of the fabricated DG-MOSFETs with good electrical characteristics. However, it is very difficult to fabricate such good DG-MOSFETs, so that device parameter extraction of the fabricated DG-MOSFETs has been [...]

Month: May 2005