Nanoelectronics – Page 82 – TechConnect Briefs

Modeling of On-Chip Simultaneous Swithcing Noise in VDSM CMOS Circuits

Tang K.T., Friedman E.G., University of Rochester, US

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on [...]

A Novel Method for the De-Embedding of S-Parameters of Double Heterojunction d-doped PHEMTs – Modeling and Measurements

Rao R.V.V.V.J., Joe J., Chia Y.W.M., Ang K.S., Wang H., Ng G.I., National University of Singapore, SG

A simple and accurate method for extracting small-signal signal equivalent circuit for double heterojunction d-doped PHEMTs was developed. The circuit elements were extracted from the S-parameters of PHEMTs. Parasitic inductances Lg, Ld and Ls were [...]

Verilog-AMS Eases Mixed Mode Signal Simulation

Miller I., Cassagnes T., Motorola ESD Europe, US

The ability to design and verify mixed mode (digital, analog, electrical, and non-electrical) systems is key to the development of new products for the ever expanding electromechanical market. Although there are several individual point tools [...]

Compact Modeling for Deep Submicron Devices

Modeling On-Currents for n-MOSFETs: Ultimate Limits vs. the NTRS

Assad F., Ren Z., Vasileska D., Datta S., Lundstrom M.S., Purdue University, US

The continued evolution of Si technology hinges to a large extent on the ability to maintain high on-currents while achieving low off-currents. As we move from sub-micron to nanoscale technology, it is not at all [...]

An Overview of the 3D Simulation Efforts at Arizona State University Directed Towards Understanding Transport in the Quantum Dots and the Ultra-Small Devices of the Future

Akis R., Vasileska D., Ferry D.K., Arizona State University, US

A brief summary of some of the simulation efforts within the Nanostructure Research Group at Arizona State University is presented, with emphasis on the tools used for modeling deep-submicrometer devices and quantum dot structures under [...]

Topic: Nanoelectronics

Modeling of On-Chip Simultaneous Swithcing Noise in VDSM CMOS Circuits

A Novel Method for the De-Embedding of S-Parameters of Double Heterojunction d-doped PHEMTs – Modeling and Measurements

Verilog-AMS Eases Mixed Mode Signal Simulation

Compact Modeling for Deep Submicron Devices

Modeling On-Currents for n-MOSFETs: Ultimate Limits vs. the NTRS

An Overview of the 3D Simulation Efforts at Arizona State University Directed Towards Understanding Transport in the Quantum Dots and the Ultra-Small Devices of the Future

Full-Band Cellular Automata for Modeling Transport in Sub-Micrometer Devices

Simulation Study of ZnTe-CdZnTe Based Asymmentric Step Strained Layer Quantum Well Infrared Photo-Detectors

Complex Potentials, Dissipative Processes and General Quantum Transport

Quantum Device Modeling