Modeling of On-Chip Simultaneous Swithcing Noise in VDSM CMOS Circuits

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On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped

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Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
Published: March 27, 2000
Pages: 313 - 316
Industry sector: Sensors, MEMS, Electronics
Topicss: Compact Modeling, Nanoelectronics
ISBN: 0-9666135-7-0