Compact Modeling – Page 10 – TechConnect Briefs

Effective Drive Current in CMOS Inverters for Sub-45nm Technologies

Hu J., Park J-E, Freeman G., Wong H.S.P., Stanford University, US

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average [...]

Modeling of gain in advanced CMOS technologies

Spessot A., Gattel F., Fantini P., Marmiroli A., STMicroelectronics, IT

The impressive downscaling of CMOS technology and its more and more massive introduction in System-on-chip (SoC) oriented applications require comprehensive modeling approach able to describe such different world (digital and analog) starting from a single [...]

Model Implementation for Accurate Variation Estimation of Analog Parameters in Advanced SOI Technologies

Suryagandh S., Subba N., Wason V., Chiney P., Wu Z-Y, Chen B.Q., Krishnan S., Rathor M., Icel A., Advanced Micro Devices, US

Analog design uses transistors with longer channel length for high performance. gm, Rout and intrinsic gain form the matrix to gauge this performance. It is critical to design these circuits for manufacturing variability. This work [...]

Modeling of Spatial Correlations in Process, Device, and Circuit Variations

Lu N., IBM, US

We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA approach, we give a very compact expression to [...]

An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles

Kaur R., Chaujar R., Saxena M., Gupta R.S., University of Delhi, IN

Since past three decades, in the pursuit of superior performances relative to high-speed circuits and packing density, miniaturization of device dimensions has been adopted as a powerful tool. Gradually, as device feature sizes move into [...]

Compact Modeling of Noise in non-uniform channel MOSFET

Roy A.S., Enz C.C., Lim T.C., Danneville F., CSEM & EPFL, CH

Compact MOSFET noise models are mostly based on the Klaassen-Prins (KP) method. However, the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional KP based methods which, at [...]

An Accurate and Versatile ED- and LD-MOS Model for High-Voltage CMOS IC Spice Simulation

Tudor B., Wang J.W., Hu B.P., Liu W., Lee F., Synopsys, Inc., US

The paper presents a high-voltage compact MOSFET model that has been proven physically accurate and numerically robust for various and generations of high-voltage ED (extended drain) and LD (laterally double diffused) production CMOS process technologies. [...]

The Bipolar Field-Effect Transistor Theory (B. Latest Advances)

Sah C-T, Jie B.B., University of Florida, US

Latest advances are presented on theoretical device and circuit characterizations of the Bipolar Field effect transistor (BiFET) [1]. The 2 Dimensional (2 D) rectangular geometry of the transistor (uniform in the width direction) is employed [...]

The Bipolar Field-Effect Transistor Theory (A. Summary of Recent Progresses)

Jie B.B., Sah C-T, Peking University, CN

Field effect transistor (FET) was conceived 80 years ago in Lilienfeld ‘s 1926 1932 patents [1]. Shockley 1952 [2] invented the volume channel FET 55 years ago using two opposing p/n junctions as gates on [...]

Improved layout dependent modeling of the base resistance in advanced HBTs

Lehmann S., Schroter M., University of Technology Dresden, DE

Existing equations for describing the layout dependent base resistance are improved and extended for heterojunction bipolar transistors (HBTs) in advanced process technologies. The new equations have been developed using quasi-3D device simulation and have been [...]