MOSFET’s – Page 2 – TechConnect Briefs

Modeling of Nanoelectronic and Quantum Devices

Ferry D.K., Akis R., Gilbert M.J., Speyer G., Arizona State University, US

The semiconductor industry is constantly pushing towards ever smaller devices and it is expected that we will see commercial devices with gate lengths less than 10 nm within the next decade. Such small devices have [...]

The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation

Xi X., He J., Heyderi B., Dunga M., Lin C.H., Heyderi B., Wan H., Chan M., Niknejad A.M., Hu C., University of California at Berkeley, US

This paper describes the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate non-charge-sheet based physics, completely continuous current and derivatives, and extendibility to non-traditional CMOS based [...]

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from the Accumulation to Depletion Region

He J., Xi X., Chan M., Cao K., Niknejad A., Hu C., University of California-Berkeley, US

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFETs Operation from Strong Accumulation to Depletion region Jin He*+, Xuemei Xi*, Mansun Chan*, and Chenming Hu* (*Electronics Research Laboratory, Department of Electrical Engineering and Computer [...]

An Advanced Surface-Potential-Plus MOSFET Model

He J., Xi X., Chan M., Niknejad A., Hu C., University of California at Berkeley, US

Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet approximation, uses the quasi-Fermi-potential to integrate drift and diffusion current and formulates an inversion charge equation that can be analytically solved for given terminal [...]

The Use of Quantum Potentials for Confinement in Semiconductor Devices

Asenov A., Brown A.R., Watling J.R., Glasgow University, UK

As MOSFETs are scaled into sub 100 nm (decanano) dimensions, quantum mechanical confinement and tunnelling start to dramatically affect their characteristics. In this paper we describe the introduction of quantum corrections within a 3D drift [...]

The Role of the Quantization Effects on the Operation of 50 nm MOSFET and 250 nm FIBMOS Devices

Vasileska D., Knezevic I., Akis R., Ferry D.K., Arizona State University, US

We investigate quantum-mechanical space quantization effects in conventional MOSFET devices and asymmetric device structure fabricated via focused ion beam technique (FIBMOS device). We find that the inclusion of the quan-tum-mechanical space-quantization effects along the growth [...]

The Use of Quantum Potentials for Confinement in Semiconductor Devices

Asenov A., Brown A.R., Watling J.R., Glasgow University, UK

As MOSFETs are scaled into sub 100 nm (decanano) dimensions, quantum mechanical confinement and tunnelling start to dramatically affect their characteristics. In this paper we describe the introduction of quantum corrections within a 3D drift [...]

A New Approach for the Extraction of Threshold Voltage for MOSFET’s

Wong J.S., Ma J.G., Yeo K.S., Do M.A., Nanyang Technological University, SG

A new approach for the extraction of threshold voltage (Vth) is proposed, namely, the "Third Derivative of Drain-Source Current" method or simply "TD" method. This method extracts the Vth by finding the Vgs where the [...]