MOSFET – Page 10 – TechConnect Briefs

Modelling of the “Gated-Diode” Configuration in Bulk MOSFET’s

Yip A., Yeow Y.T., Samudra G.S., Ling C.H., TECH Semiconductor, SG

A study of the “gated-diode” configuration in MOSFET’s for characterising hot-carrier degradation by employing 2-D simulations is presented in this paper. We use both process and device simulations to understand operational sensitivity of this technique. [...]

A New Continuous Model for Deep Submicron MOSFETs

Chan K-M.S., Wong N-C.A., Wong S-C., Chao C-J., Kao D-B., Wong N-C.A., Wong S-C., Yang C.Y., Winbond Electronics Corporation America, US

A 1-D model is developed to account for mobile charges in the Source/Drain junction regions of a MOSFET. 2-D effects such as Threshold Roll-off and Drain Induced Barrier Lowering are accounted for with an empirical [...]

A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET’s Technology Development and Circuit Simulation

Zhou X., Lim K.Y., Nanyang Technological University, SG

This paper presents a novel approach to formulating compact I-V models for deep-submicron MOS technology development. The developed model is a one-region closed-form equation that resembles the same form as the long-channel one, which covers [...]

Modeling of Threshold Voltage with Reverse Short Channel Effect

Lim K.Y., Zhou X., Wang Y., Nanyang Technological University, SG

This paper presents a new reverse short channel effect (RSCE) model for threshold voltage modeling of submicrometer MOSFETs. Unlike those conventional empirically-based RSCE models, the proposed model is derived and simplified based on two Gaussian [...]

Closed-Loop MOSFET Doping Profile Optimization for Portable Systems

Stockinger M., Strasser R., Plasun R., Wild A., Selberherr S., TU Vienna, AT

We present a new closed-loop simulation-based optimization process for a 100 nm MOSFET for portable systems such as subscriber units for wireless communications, yielding an almost double drive performance at equivalent stand-by power when compared [...]

A Compact Model for an IC Lateral Diffused MOSFET Using the Lumped-Charge Methodology

Subramanian Y., Lauritzen P.O., Green K.R., Texas Instruments, US

A compact model for an IC Lateral Diffused MOSFET is developed using the Lumped-Charge Methodology[1]. Model equations and key performance characteristics are documented. They satisfy the requirements of Power MOSFET models[2], unlike the competitive macromodels [...]

Cellular Automata Studies of Vertical MOSFETs

Saraniti M., Wigger S., Zandler G., Formicone G., Goodnick S.M., Arizona State University, US

This paper presents an overview of the cellular automata (CA) method for semiconductor device simulation. The main advantages of the CA method over the Monte Carlo (MC) approach are presented, and limitations of its modeling [...]

A Method of MOSFET Dopant Profile Prediction and its Use in Transistor Design

Kulkarni M., Vasanath K., Davis J., Saxena S., Pollack G., Texas Instruments, Inc., US

As MOS transistor size shrinks to sub-quartermicron dimensions, accurate knowledge of the dopant concentration in various regions of the transistor is becoming more and more important for device simulations. We have developed a methodology to [...]