FinFET – Page 3 – TechConnect Briefs

Modeling of Saturation-Region Characteristics of Nanoscale Double-Gate MOSFETs

Fossum J.G., Chouksey S., University of Florida, US

Saturation-region effects, unique to double-gate (DG) MOSFETs, are discussed and modeled in UFDG. The effects include carrier velocity overshoot and drain-induced charge enhancement (DICE). The former, modeled in terms of carrier temperature, implies ballistic-like currents [...]

Optimization and Examination of Device Characteristics Due to Process Variation in 10 nm FinFET Using Fully Self-Consistent Quantum Mechanical Simulator

Khan H., Mamaluy D., Vasileska D., Arizona State University, US

We use Contact Block Reduction (CBR)method to investigate the critical issues relating optimization of device performance in 10 nm FinFET operating in ballistic regime. The goal of this work is to achieve the desired values [...]

Self-consistent Quantum Mechanical Treatment of the Ballistic Transport in 10 nm FinFET Devices Using CBR Method

Khan H., Mamaluy D., Vasileska D., Arizona State University, US

CBR technique has been used to perform fully quantum-mechanical simulation of 10nm FinFET devices with varying fin width. Device characteristics have been observed and compared to the experimental values. It is observed from the simulation [...]

Examination of the Effects of Unintentional Doping on the Operation of FinFETs with Monte Carlo Simulation Integrated with Fast Multipole Method (FMM)

Khan H., Ahmed S.S., Vasileska D., Arizona State University, US

Novel device structures such as dual gate SOI, Ultra thin body SOI, FinFETs, etc. have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. In this paper, we use a semi-classical [...]

2D Quantum Mechanical Device Modeling and Simulation: Single and Multi-fin FinFET

Kim K., Kwon O., Seo J., Won T., Inha University, KR

A two-dimensional quantum mechanical modeling has been performed to simulate a nano-scale FinFET by obtaining the self-consistent solution of coupled Poisson and Schrödinger equations. Calculated current-voltage (I-V) curves are carefully compared with experimental data to [...]

Atomistic Process and Simulation in the Regime of sub-50nm Gate Length

Kwon O., Kim K., Seo J., Won T., Inha University, KR

In this paper, we report an atomistic simulation approach for sub-50nm gate length FETs. The proposed atomistic approach consists of the coupling the molecular dynamics (MD) simulations of the collision cascades for ion implantation process [...]

Double-Gate CMOS Evaluation for 45nm Technology Node

Chiang M-H, An J.X., Krivokapic Z., Yu B., AMD, US

Interest in the double-gate (DG) MOSFET has been growing as transistor development is approaching the end of SIA roadmap. Recent progress in DG technology, and some theoretical study have promoted DG to one of the [...]