double-gate – Page 3 – TechConnect Briefs

Three-Dimensional Simulation of Polysilicon Thin Film Transistors with Single-, Double-, and Surrounding-Gate Structures

Li Y., Lee B-S, National Chiao Tung University, TW

Thin-film-transistors (TFTs) with high mobility and low leakage current are desirable in many applications especially in liquid crystal display (LCD).We have computationally analyzed electrical properties of thin film transistors using three-dimensional (3D) simulation. It is [...]

Compact, Physics-Based Modeling of Nanoscale Limits of Double-Gate MOSFETs

Chen Q., Wang L., Murali R., Meindl J.D., Georgia Institute of Technology, US

Compact, physics-based models of subthreshold swing and threshold voltage are presented for double-gate (DG) MOSFETs in symmetric, asymmetric, and ground-plane modes. Applying these device models, threshold voltage variations in DG MOSFETs are comprehensively and exhaustively [...]

Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology (AIST), JP

We have proposed a compact model of the DG MOSFETs which handles two gates independently. The model can simulate the DG MOSFETs of asymmetric gate design, together with their four-terminal operation. In this report, we [...]

Random Dopant Induced Fluctuations of Characteristics in Deep Sub-micron MOSFETs

Chou H-M, Lo S-C, Tsai J-H, Li Y., NCHC, TW

As the gate length of MOSFET devices shrinks down below 100 nm, the fluctuation of major devices parameter, namely, threshold voltage (VTH), subthreshold swing, drain current (ID) and subthreshold leakage current duo to influences of [...]

A Study of the Threshold Voltage Variations for Ultra-thin Body Double Gate SOI MOSFETs

Tang C-S, Lo S-C, Lee J.W., Tsai J-H, Li Y., Natl Nano Device Labs & Natl Chiao Tung Univ, TW

Double gate silicon on insulator (SOI) devices are more and more attractive for sub-50 nm ultra-large scaled integrated (ULSI) circuits manufacturing. The double gate SOI devices, owing to a difficulty of manufacturing uniformity, suffer fluctuations [...]

Improved Compact Model for Four-Terminal DG MOSFETs

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology, JP

Double-gate field-effect transistors are promising device structures which have excellent scalability. To evaluate merits of DG MODFETs, we developed a compact four-terminal DG MOSFET model by adopting the double charge-sheet model. In this presentation, we [...]

Compact, Physics-Based Modeling of Nanoscale Limits of Double-Gate MOSFETs

Chen Q., Wang L., Murali R., Meindl J.D., Georgia Institute of Technology, US

Compact, physics-based models of subthreshold swing and threshold voltage are presented for double-gate (DG) MOSFETs in symmetric, asymmetric, and ground-plane modes. Applying these device models, threshold voltage variations in DG MOSFETs are comprehensively and exhaustively [...]

Impact of Quantum Mechanical Tunnelling on Off-leakage Current in Double-gate MOSFET using a Quantum Drift-diffusion Model

Jaud M-A, Barraud S., Le Carval G., CEA-LETI, FR

With the growing use of wireless electronics systems, off-state leakage current in MOSFETs appears as one of the major physical limitations. Measurements of quantum tunnel current between source-drain (S?D) have recently shown that it will [...]

Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode

Nakagawa T., Sekigawa T., Tsutsumi T., Suzuki E., Koike H., Electroinformatics Group, AIST, JP

Recently, a double-gate structure has attracted much attention as an emerging device concept. The DG MOSFET is regarded as the most scalable device. Usually the DG MOSFET is supposed to be used as a three-terminal [...]

Double-Gate CMOS Evaluation for 45nm Technology Node

Chiang M-H, An J.X., Krivokapic Z., Yu B., AMD, US

Interest in the double-gate (DG) MOSFET has been growing as transistor development is approaching the end of SIA roadmap. Recent progress in DG technology, and some theoretical study have promoted DG to one of the [...]