DIBL – TechConnect Briefs

Impact of High-k gate oxide on intrinsic device Performance of Junctionless Transistor (JLT)

Borse H.S., Jawake A.V., Aher S.R., Bhosale K.S., Patil G.C., Patil S.R., Patil G.C., Patil S.R., Bormane D.S., JSPM’s Rajarshi Shahu College of Engineering, IN

Junctionless transistor (JLT) attracts the researchers due to its advantages over conventional MOSFET’s namely high scalability, simple process flow, and low thermal budget. However, scaling of JLT below 20 nm regime results increase in off [...]

Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs

Karim M.A., Venugopalan S., Chauhan Y.S., Lu D., Niknejad A., Hu C., University of California at Berkeley, US

MOSFET intrinsic capacitances going negative is a major concern in the compact model community. Negative Intrinsic Capacitances (NIC) can raise non-convergence issues in circuit simulators. In some cases NICs can be explained using physical phenomena. [...]

Process Factors in the Reduction of Output Conductance in Sub-micron CMOS

May N.C., Tan H.S., Kordesch A.V., SILTERRA (M) SDN BHD, MY

CMOS Analog circuits require transistors with low output conductance (gds) in order to achieve high gain. Submicron MOSFETs with halo implants and retrograde wells are designed to have high transconductance (gm) but often suffer from [...]