US – Page 461 – TechConnect Briefs

Monte-Carlo Simulation of GaAs Devices Using High Generality Object-Oriented Code and Encapsulated Scattering Tables

Harris J., Vasileska D., Arizona State University, US

Many factors are responsible for the continued shift in industry prototyping preference from device fabrication to device simulation. One of the incentives for this transition is the generality and flexibility gained by avoiding a physical [...]

Optimization of FIBMOSs through 2-D Device Simulations

Kang J., Schroder D.K., Pivin D.P., Arizona State University, US

Channel engineering can enhance the performance of MOSFETs. Focused ion beam (FIB) implant technology is one approach for such channel engineering. We have investigated FIB and present a sophisticated optimization technique for FIB MOSFETs (FIBMOS) [...]

Mobility Degradation and Current Loss Due to Vertical Electric Field in Channel Area of Submicron MOS Devices

Keshavarz A.A., Walters J.L., Sampson R., STMicrolectronics, US

In this work we show quantified modeling results for the effect of gate-voltage-induced mobility degradation on MOS device current. Presented results are for three technologies, i.e. 0.50 mm, 0.35mm, and 0.25mm, and are based on [...]

A New Continuous Model for Deep Submicron MOSFETs

Chan K-M.S., Wong N-C.A., Wong S-C., Chao C-J., Kao D-B., Wong N-C.A., Wong S-C., Yang C.Y., Winbond Electronics Corporation America, US

A 1-D model is developed to account for mobile charges in the Source/Drain junction regions of a MOSFET. 2-D effects such as Threshold Roll-off and Drain Induced Barrier Lowering are accounted for with an empirical [...]

Genetic Algorithm Based MOSFET Model Parameter Extraction

Keser M., Joardar K., Motorola SPS, US

The Levenberg-Marquardt (LM) minimization algorithm commonly employed in MOSFET model parameter extraction has several known deficiencies, such as poor convergence characteristics without a good initial guess, low likelihood of convergence to the globally optimal solution, [...]

Automatic Generation of Equivalent Circuits from Device Simulation

Pacelli A., Mastrapasqua M., Alam M.A., Luryi S., Bell Laboratories, Lucent Technologies, US

We present a novel methodology for the direct extraction of equivalent circuit models from device simulation. The circuit topology is physically based, i.e., each voltage node corresponds to a quasi-Fermi level or to an electrostatic [...]

Analytical Results for the Current-Voltage Characteristics of an SOI-MOSFET

Morris H.C., Cumberbatch E., Phillips T., Hinderberger B., Claremont Graduate University, US

Exact formulae for the current-voltage characteristics of an SOI/SOS MOSFET operating in the fully depleted mode are derived by extending the asymptotic method of Ward [1,2]. A detailed comparison with test data is presented and [...]

Modeling of On-Chip Simultaneous Swithcing Noise in VDSM CMOS Circuits

Tang K.T., Friedman E.G., University of Rochester, US

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on [...]

Verilog-AMS Eases Mixed Mode Signal Simulation

Miller I., Cassagnes T., Motorola ESD Europe, US

The ability to design and verify mixed mode (digital, analog, electrical, and non-electrical) systems is key to the development of new products for the ever expanding electromechanical market. Although there are several individual point tools [...]

Simulating IMD in SiGe HBTs: How good are our models?

Wong P., Pejcinovic B., Portland State University, US

Nominal transistor model parameters are found to be insufficient for reliably predicting intermodulation distortion (IMD) in heterojunction bipolar transistors. A method for optimizing the model parameters to give a more accurate simulation of IMD performance [...]