US – Page 352 – TechConnect Briefs

Fabrication and Transistor Demonstration on Si-based Nanomembranes

Yuan H-C, Roberts M.M., Savage D.E., Lagally M.G., Ma Z., Celler G.K., University of Wisconsin-Madison, US

We demonstrate the fabrication of free standing Si, SiGe, and Si/SiGe/Si membranes and the ability to transfer them onto various kinds of host substrates. In addition to the unstrained Si, SiGe membranes, strained Si is [...]

Self-consistent Quantum Mechanical Treatment of the Ballistic Transport in 10 nm FinFET Devices Using CBR Method

Khan H., Mamaluy D., Vasileska D., Arizona State University, US

CBR technique has been used to perform fully quantum-mechanical simulation of 10nm FinFET devices with varying fin width. Device characteristics have been observed and compared to the experimental values. It is observed from the simulation [...]

Deformation of Nanocrystalline Metals under Nanoscale Contact

Sansoz F., Dupont V., The University of Vermont, US

The nanoindentation of a columnar grain boundary (GB) network in nanocrystalline Al has been examined by atomistic simulation. Our intent was to gain fundamental understanding on the relationship between structure evolution at GBs and incipient [...]

Active Coatings Technologies for Customized Military Coating Systems

Zunino III J.L., U.S. Army ARDEC, US

The main objective of the U.S. Army’s Active Coatings Technologies Program is to develop technologies that can be used in combination to tailor coatings for utilization on Army Materiel. The Active Coatings Technologies Program, ACT, [...]

A History of MOS Transistor Compact Modeling

Sah C-T, University of Florida, US

The MOSFET (Metal-Oxide-Silicon Field-Effect- Transistor) or MOS Transistor (MOST) is a three dimensional electronic device. It operates on the conductivity modulation principle in a thin semiconductor layer by a controlling electric field to give amplifying [...]

Vector Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance

Pacelli A., SUNY-Stony Brook, US

We present a compact topology for inductive parasitics, using the vector potential as a state variable. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range [...]

Compact Modeling for RF and Microwave Integrated Circuits

Niknejad A.M., Chan M., Hu C., Brodersen B., Xi J., He J., Emami S., Doan C., Cao Y., Su P., Wan H., Dunga M., Lin C.H., University of California at Berkeley, US

Compact modeling has been an integral part of the design of integrated circuits for digital and analog applications. The availability of scalable CMOS device models has enabled rapid simulation and design of present and future [...]

BJT Modeling with VBIC, Basics and V1.3 Updates

McAndrew C., Bettinger T., Lemaitre L., Tutt M., Motorola, US

This paper reviews the VBIC BJT model, and details updates in the version 1.3 release. VBICv1.3 includes explicit interaction with siulator global parameters gmin and pnjmaxi, explicit limiting of local temperature rise and exponential arguments [...]

A Physics-Based Compact Model for Nano-Scale DG and FD/SOI MOSFETs

Fossum J., Ge L., Chiang M-H, University of Florida, US

A process/physics-based compact model (UFDG) for double-gate (DG) MOSFETs is overviewed. The model, in essence, is a compact Poisson-Schrödinger solver, including accountings for short-channel effects, and is applicable to nano-scale fully depleted (FD) SOI MOSFETs [...]

An Advanced Surface-Potential-Plus MOSFET Model

He J., Xi X., Chan M., Niknejad A., Hu C., University of California at Berkeley, US

Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet approximation, uses the quasi-Fermi-potential to integrate drift and diffusion current and formulates an inversion charge equation that can be analytically solved for given terminal [...]