Papers – Page 11 – TechConnect Briefs

An SOA Aware MOSFET Model for Highly Integrated, Analog Mixed-Signal Design Environments

Hall J., Luo Z., Xiao Y., Young A., Connerney D., Fairchild Semiconductor, US

Circuit simulations involving power devices often require additional checks comparing with generic low power applications. The burden lies with the individual designers to ensure that the power transistors are operating well within the Safe Operating [...]

SPICE BSIM3 Model Parameters Extraction and Optimization for Low Temperature Application

Abebe H., Tyree V., Cockerham N.S., USC/ISI MOSIS, US

The SPICE BSIM3v3.1 model parameters extraction and optimization strategy that we present here is applicable for a half micron technology and circuits operating at temperature ranging from -191 to 125 0C. The room temperature extraction [...]

A Simple, Accurate Capacitance-Voltage Model of Undoped Silicon Nanowire MOSFETs

Lin S., Zhou X., See G.H., Zhu G., Wei C., Zhang J., Chen Z., Nanyang Technological University, SG

Gate-All-Around (GAA), or surrounding-gate, MOSFET is one of the most promising structures beyond bulk CMOS. In this paper, we present a simple, accurate C-V model of undoped silicon nanowire MOSFETs. Different with other models, proposed [...]

1/f Noise Model for Double-Gate FinFET Biased in Weak Inversion

Wei C.Q., Xiong Y.Z., Zhou X., Nanyang Technological University, SG

1/f noise model of long channel lightly-doped FinFET biased in weak inversion has been described using Hooge’s theory. From the drain current equation and the channel conductance expression, the total number of carriers under the [...]

1/f Noise Modeling at Low Temperature with the EKV3 Compact Model

Martin P., Ghibaudo G., CEA/LETI/MINATEC, FR

Advanced compact models are mandatory for simulation of mixed analog-digital circuits working at low temperature (77-200 K). In this work, the 1/f noise model introduced in the EKV3 model is evaluated. This evaluation is performed [...]

Compact Model of Low – Frequency Noise in Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

Miller D.A., Jacob M.E., Forbes L., Oregon State University, US

At nanoscale device dimensions low frequency noise is dominated by one or more oxide traps capturing and emitting charge and generating large swings in the drain current or what is known as Random Telegraph Signal [...]

RF Modeling of 45nm Low-Power CMOS Technology

Wang J., Li H., Pan L.H., Gogineni U., Groves R., Jagannathan B., Na M-H, Tonti W., Wachnik R., IBM Semiconductor Research and Development Center, US

As CMOS has grown to be one of the principle technologies for RF IC design, accurate modeling of MOSFETs at high frequencies becomes increasingly important. In this paper, we present an advanced RF modeling work [...]

Numerical Study of Carrier Velocity for P-type Strained Silicon MOSFET

Heong Y.W., Ahmadi M.T., Suseno J.E., Ismail R., Universiti Teknologi Malaysia, MY

Abstract In this paper, a numerical study of carrier concentration for P-type strained Silicon MOS is presented. Density of state proportion of Fermi-Dirac intergral that covers the carrier statistics to all degenerate level is studied [...]

PSP Model Equations Extension for Statistical Estimation of Leakage Current in Nanometer CMOS Technologies Considering Process Variations

D’Agostino C., Flatresse P., Beigne E., Belleville M., STMicroelectronics, FR

A novel analytical methodology is proposed for statistical leakage estimation of CMOS circuits considering statistical process variations. The goal of the proposed methodology is to obtain a time-efficient and accurate estimation of the PDF of [...]

Elements of Statistical SPICE Models

Lu N., Watts J., Springer S.K., IBM, US

We discuss several elements of statistical SPICE models and present our solutions. We present (i) a solution of automatically detecting Monte Carlo vs. skewed simulations, (ii) a method of modeling an arbitrarily given asymmetric or [...]