Nanoelectronics – Page 84 – TechConnect Briefs

Hierarchical Approach to Simulation in a Vertical System for the TriCore Microcontroller

Salzmann C., Chesters E., Coelho P., Fu Y-C, Madala J., Reddy M., Wang F., Siemens Microelectronics, Inc., US

This paper describes a hiercihical functional verification system for a core-based system design which minimizes complexity in testbenches while maximizing flexibility in terms of number of clocks and system interfaces and reducing time-to-market. The verification [...]

Simulations of a New CMOS Compatible Method to Enhance the Breakdown Voltage of Highly-Doped Shallow PN Junctions

Pauchard A., Besse P.A., Popovic R.S., EPFL, CH

Avalanche breakdown often limits the working range of planar junction diodes in electronic circuits and in sensors. We present two-dimensional device simulation results (using MEDICI) of a novel CMOS compatible structure. It combines a floating [...]

Concurrent Process, Device and Integrated Circuit Development by Predictive Engineering for Smart Power Technologies

Bafleur M., Dinh T., Park H., Thoma R., Zirkle T., Wild A., LAAS/CNRS, FR

Predictive TCAD has been shown to be a powerful tool for the development of low voltage CMOS and VLSI memory technology development [1], [2] in which the main features of advanced p-channel and n-channel MOS [...]

The Influence of Space Quantization Effect on the Threshold Voltage, Inversion Layer and Total Gate Capacitance in Scaled Si-MOSFETs

Vasileska D., Ferry D.K., Arizona State University, US

We investigate the influence of poly-gate depletion on the inversion layer capacitance CinV, total gate capacitance CtOt and threshold voltage VT in scaled Si MOSFETs using both semiclassical (SC) and quantum-mechanical (QM) description of the [...]

Topic: Nanoelectronics

Hierarchical Approach to Simulation in a Vertical System for the TriCore Microcontroller

Simulations of a New CMOS Compatible Method to Enhance the Breakdown Voltage of Highly-Doped Shallow PN Junctions

Concurrent Process, Device and Integrated Circuit Development by Predictive Engineering for Smart Power Technologies

The Influence of Space Quantization Effect on the Threshold Voltage, Inversion Layer and Total Gate Capacitance in Scaled Si-MOSFETs

Applications: Semiconductors