Compact Modeling – Page 4 – TechConnect Briefs

Analytical Solutions to Model the Line Edge Roughness and its Effect on Subthreshold Behavior of DG FinFETs

Monga U., Fjeldly T.A., Norwegian University of Science and Technology, and University Graduate Center (UNIK), NO

Statistical variability such as line edge roughness (LER) and random dopant effects have become major concerns in the nanoscale regime. Due to the intrinsic body, multigate devices such as FinFETs don’t suffer from random dopant [...]

Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling

Abebe H., Cumberbatch E., USC/ISI, US

We have developed a surface potential based compact model for a single well semiconductor CNT field effect transistor. Our compact modeling results for surface potential, channel charge, gate capacitance and channel current are compared with [...]

The accurate Electro-Thermal Model of Merged SiC PiN Schottky Diodes

Zubert M., Starzak L., Jablonski G., Napieralska M., Janicki M., Napieralski A., Technical University of Lodz, PL

This paper presents a novel SPICE model for SiC merged PiN Schottky diodes dedicated to the dynamic, as well as to very accurate static simulation. The model takes into account the temperature dependence of device [...]

Characterization and Modeling of Metal Finger Capacitors

Lu N., Booth R., Daley D., Thompson E., Putnam C., IBM, US

A capacitor solution with no mask or process additions can be formed by the use of interdigitated metal fingers. Often, this metal finger capacitor uses multiple back-end-of-line (BEOL) levels to increase capacitance density. Metal structures [...]

Modeling Bias Stress Effect on Threshold Voltage for Amorphous Silicon Thin-Film Transistors

Shen C-H, National Chiao Tung University, TW

Amorphous silicon thin-film transistors (a-Si:H TFTs) are widely used in active-matrix backplanes for LCD displays on glass. Unfortunately, DC and dynamic characteristics of a-Si:H TFTs are sensitive [1]; in particular, they suffer form electric-field-induced threshold [...]

Charge Partition in Lateral Nonuniformly-Doped Transistor

Zhang J., Zhou X., Zhu G., Lin S., Nanyang Technological University, SG

In this work, we aim to model the LDMOS capacitance behavior of the core channel. In order to simplify the problem, the diffused doping profile in the core channel is approximated as a step profile. [...]

Modeling of the impurity-gradient effect in high-voltage MOSFETs

Maekawa Y., Fukushima K., Tanaka A., Kikuchihara H., Miyake M., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP

Two major high-voltage MOSFET types are commonly used by semiconductor industries. One has a symmetrical structure, and the other has a laterally-diffused asymmetric structure called LDMOS. Here our focus is the LDMOS structure, where an [...]

Analytic potential model for asymmetricunderlap gate-all-around MOSFET

Wang S., Peking University, CN

An analytic potential model for undoped cylindrical gate-all-around (GAA) MOSFET with asymmetric gate underlap is developed in this paper. This model is derived by solving the Poisson’s equation with the parabolic potential approximation, channel length [...]

HiSIM-DG for Extracting Statistical Variations of Measured I-V Characteristics

Shintaku Y., Hiroshima University, JP

The variability of the DG-MOSFET is expected to cause serious problems for real circuit applications. Thus purpose of our investigation is to provide an accurate extraction of device variations, and to predict influence of the [...]

Comparison and insight into long-channel MOSFET drain current models

Zhang L., Peking University, CN

In this paper we provide an insight into the drain current model for long-channel MOSFET devices. A new method to perform the integral of the rigorous Pao-Sah dual integral current is derived. From it, we [...]