A capacitor solution with no mask or process additions can be formed by the use of interdigitated metal fingers. Often, this metal finger capacitor uses multiple back-end-of-line (BEOL) levels to increase capacitance density. Metal structures at different BEOL levels are connected using vias between tabs, and vias may also directly connect fingers of two adjacent BEOL levels. Metal finger capacitors are used in a variety of VLSI circuits (e.g., analog-to-digital converters). We discuss the characterization and modeling of metal finger capacitors and show a more accurate approach to extract capacitance density from measured data or from a SPICE model of a metal finger capacitor. When technology rules allow a metal finger capacitor to use the first K BEOL levels of a semiconductor technology, we first show a set of capacitance relations, and then show a smarter way to cover K(K+1)/2 possible level combinations of the metal finger capacitor using only (2K–1) level combinations in semiconductor physical test structures. We present our compact models of metal finger capacitors, which include various capacitance components (electric field lines in via space, field lines above the top level of a capacitor, and field lines below the bottom level of a capacitor) and the modeling of the effective resistance of the capacitor.
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 13, 2011
Pages: 792 - 795
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling