Advanced Manufacturing – Page 50

Hole Transport Simulations in p-channel Si MOSFETs

Krishnan S., Vasileska D., Fischetti M.V., Arizona State University, US

We use a Monte Carlo method to investigate hole transport in ultrasmall p-channel MOSFETs with gate lengths of 25 nm. To model band-structure effects like warping, anisotropy and non-parabolicity on carrier transport, our device simulator [...]

SOS Gate Capacitance Modeling

Morris H.C., Cumberbatch E.C., Abebe H., San Jose State University, US

A gate capacitance model for the SOS structure has been developed. The spatial dependence of the potential defines the changes in the charge density as well as the boundary conditions between the layers. The SOS [...]

MOSFET Analytical Inversion Charge Model with Quantum Effects using a Triangular Potential Well Approximation

Abebe H., Cumberbatch E.C., Tyree V., Morris H.C., USC/ISI MOSIS, US

The eigenfunctions from solutions of the Schrödinger equation for a triangular potential well are the Airy functions. The triangular potential approximation has been shown to be a good approximation for the charge density when the [...]

Controllable Electron Transport in the Lateral Nanostructure

Pogrebnyak V.A., Akray E., Küçükaltun A.N., Cukurova University, TR

The study of two-dimensional electronic systems evokes considerable interest due to the broad utilization of the systems in nanotechnology. Design of new devices are commonly based on exploiting the different configurations of multiple-quantum-well (MQW) structures. [...]

Analytical Surface Potential Model with Polysilicon Gate Depletion Effect for NMOS

Cumberbatch E., Abebe H., Morris H., Tyree V., USC/ISI MOSIS, US

Different modeling approaches for the sub-100nm MOSFET are discussed in [1] and the surface potential description model is reported to be promising, [1, 2]. Surface potential changes impact gate capacitance and current-voltage (I-V) characteristics of [...]

Mismatch Improvement with XMOS Structure

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

MOS transistor has been continuously scaled down to improve the device performance. Smaller MOS transistors have higher transconductance (gm) and low capacitance, so the ratio gm/C is improved by shrinking. Shorter gate length provides higher [...]

Electronic Properties of Gaphitic Surfaces with Adsorbed Aromatic Amino Acids

Roman C., Ciontu F., Courtois B., Tima Laboratory, FR

The electronic properties of aromatic amino acids physisorbed on graphene are investigated in view of establishing if carbon nanotube transconductance sensors can respond to this type of chemical stimuli. Several conclusions are drawn regarding both [...]

Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory Devices

Entner R., Gehring A., Kosina H., Grasser T., Selberherr S., TU Vienna, AT

In this work a new approach for modeling gate leakage currents for memory cells which are highly degraded is proposed. In thicker dielectrics which are subject to high field stress and can therefore have a [...]

Examination of the Effects of Unintentional Doping on the Operation of FinFETs with Monte Carlo Simulation Integrated with Fast Multipole Method (FMM)

Khan H., Ahmed S.S., Vasileska D., Arizona State University, US

Novel device structures such as dual gate SOI, Ultra thin body SOI, FinFETs, etc. have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. In this paper, we use a semi-classical [...]

Low Field Electron Mobility in Ultra-Thin Strained-Si Directly on Insulator MOSFET in Sub-0.1µm Regime

Amtablian S., Barraud S., CEA-DRT/LETI, FR

A 200 word (or less) text only summThe fabrication of Fully-Depleted strained-Si directly on insulator (SSOI) MOSFET was recently demonstrated. The combination of strain-induced transport property with the scaling advantage of ultra-thin body devices is [...]