Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory Devices

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In this work a new approach for modeling gate leakage currents for memory cells which are highly degraded is proposed. In thicker dielectrics which are subject to high field stress and can therefore have a high defect density, not only direct tunneling currents but also trap-assisted tunneling plays an important role. By rigorous simulation we show, for the first time, that also a multi-trap assisted tunneling component becomes important for dielectric thicknesses above approximately 3 nm and even gains importance for thicker layers.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 8, 2005
Pages: 45 - 48
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Advanced Manufacturing, Nanoelectronics
ISBN: 0-9767985-2-2