Papers – Page 976 – TechConnect Briefs

Standardization and Validation of Compact Models

Brooks B., Green K., Krick J., Vrotsos T., Weiser D., Texas Instruments, US

The idea of standardizing compact (SPICE-like) models has recently gained momentum in the semiconductor industry. However, since compact model equations reside in software, the concept of standardization is difficult. Several key issues must be addressed, [...]

Detailed Comparison of the SP2001, EKV, and BSIM3 Models

Bendix P., LSI Logic, US

Practical comparisons are made of three available or soon to be available compact MOS models----SP2001 (surface potential 2001), EKV, and BSIM3. They are compared both in their DC and AC quality of fits to measured [...]

Challenges of Modeling VLSI Interconnects in the DSM Era

Arora N.D., Simplex Solutions, US

As VLSI technology shrinks to deep sub-micron (DSM) geometries (below 0.18mm), the parasitic due to interconnects are becoming a limiting factor in determining circuit performance. An accurate modeling of interconnect parasitic resistance (R), capacitance (C) [...]

The New Approach to the Power Semiconductor Devices Modelling

Starzak L., Zubert M., Napieralski A., Technical University of Lodz, PL

Due to their specific structures the power devices need special models different from those developed for low power electronics. The development of such special models is far from being simple as distributed nature of phenomena [...]

Novel Computing Architecture on Arrays of Josephson Persistent Current Bits

Han J., Jonker P., Delft University of Technology, NL

A superconducting qubit (or quantum bit), which consists of a micrometer-sized loop with three Josephson junctions, has two persistent currents of opposite direction as its two states. The states of the qubit can be brought [...]

Characterization of “Multipath Interconnects” for Microelectronic and Nanotechnology Circuits

Goel A.K., Eady N.R., Michigan Technological University, US

A multipath interconnect carries a signal by using the concept of parallel processing by providing two or more paths between the driver and the load. These paths are stacked vertically isolated from one another by [...]

Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD)

Subramanian Y., Darling R.B., University of Washington, US

This paper presents compact, physically-based electrothermal models for direct as well as indirect bandgap tunneling processes in pn-junctions for use in network simulators (e.g. Saber or VHDL-A). The model for indirect tunneling has been validated [...]

Simulation of Heterojunction Bipolar Transistor with Domain Decomposition Method

Zhang Y., Ruden P.P., Oklahoma State University, US

Domain decomposition method is used in simulation of the band profile and the majority carrier concentration profile of AlGaN/GaN heterojunction bipolar transistors. The method is very stable and efficient. With this method different device structures [...]

Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation

Yoon S., Won T., Inha University, KR

In this paper, an approach is proposed for extracting coupled RLC network from multi-level interconnects. The proposed approach starts with a step of partitioning the layout of the full-chip under consideration into several sub-layouts, followed [...]

Physics-Based and Compact Models for Self-Heating in High-Speed Bipolar Integrated Circuits

Pacelli A., Palestri P., Mastrapasqua M., State University of New York-Stony Brook, US

We present three-dimensional heat-transport simulation for bipolar transistors. The simulations are validated on experimental data, and are employed to develop analytical models for the thermal resistance of devices fabricated on bulk and SOI substrate, and [...]