In the MEMS and MOEMS product world, manufacturer of display/micro-devices requires bonding of two wafers. The front side pattern of the top wafer needs to be aligned with aggressive overlay requirement with the remaining portion of the device that is to be patterned on the backside of the same wafer. The most important first challenge here is to devise a litho technique that will allow the alignment of layers on the backside of the wafer to the pattern on the wafer’s front surface after bonding (thereby encapsulating the patterned surface) without significant hardware changes to ensure that the resulting overlay will support the product performance specs. ASML’s Special Applications Business unit jointly with SVTC and Miradia came up with a simple but elegant lithographic technique that can be applied on ASML’s advanced litho tools as solution to this challenge. Paper will discuss the lithographics technique designed and processes developed to resolve these challemges for device production with supporting technical details and data as applicable.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 1
Published: May 20, 2007
Pages: 244 - 249
Industry sector: Advanced Materials & Manufacturing
Topics: Advanced Manufacturing, Nanoelectronics