SRAM – TechConnect Briefs

Simulation Study on Dopant Fluctuation Impact on SRG MOSFET Device and Circuit Performane

Wang H., He J., Liu Y., Peking University Shenzhen SOC Key Laboratory, CN

This paper investigates the impact of random dopant fluctuation on surrounding gate MOSFET, from atomic statistical simulation of device to circuit performance evaluation. The doping profile is generated by an analysis of each lattice atom [...]

GIDL Current and Pass-Gate Body Potential Modeling in 22nm HKMG PD-SOI CMOS

Luo L., Walko J.P., Johnson J.M., Springer S., IBM, US

In a floating PD (partially depleted) SOI (silicon-on-insulator) transistor, the internal DC body potential is determined by the various body current components, mainly including diode current, gate-to-body oxide tunneling current (Igb), impact ionization current (II) [...]

Variability Study for Silicon Nanowire FETs

Liao Y.-B., Chiang M-H, Kim K., Hsu W.-C., National Cheng Kung University, TW

3-D numerical simulation shows that both the conventional and JL nanowire FETs are sensitive to structural variation whereas the former is more tolerable. Due to more increased Ion/Ioff for lower D and WSi in JL, [...]

Performance study of Ballistic and Quasi-Ballistic on Double-Gate MOSFETs 6T SRAM cell

Martinie S., Jaud M-A, Munteanu D., Thomas O., Le Carval G., Autran J-L, CEA/LETI/MINATEC, FR

The impact of ballistic/quasi-ballistic carrier transport on the switch of a CMOS inverter and on the noise margin of a 6T SRAM cell, both based on Double-Gate MOSFETs (DGMOS), is analysed using mixed-mode simulation. To [...]

Process- and Random-Dopant-Induced Characteristic Variability of SRAM with nano-CMOS and Bulk FinFET Devices

Li T-Y, Li Y., Hwang C-H, Li T-Y, Li Y., National Chiao Tung University, TW

The magnitude of the intrinsic parameter fluctuations, such as process-variation and random dopant fluctuation, steadily increase with the reduction of device dimensions, and lead to pronounced component mismatch in area constrained circuits such as static [...]

A Simple Yet Accurate Mismatch Model For Circuit Simulation

Jin Z., Lee Y.M., Watts J.S., Bonaccio A.R., Schroer G.J., Pai N.G., IBM, US

As technology scales, mismatch between a pair of transistors becomes a more and more critical issue for technology development and circuit designs. Scaling also increases the complexity of compact device modeling. Sophisticated models are usually [...]

Three-Dimensional Effects Obtained from Capacitance Analysis of an SRAM Cell

Takemura Y., Osada K., Yagyu M., Yamaguchi K., Ushio J., Maruizumi T., Hitachi Ltd., JP

Employing Green's function method, we analyzed the 3D capacitance for the hole interconnect structure in an SRAM cell. We found novel 3D effects as follows; (1) via connection increases the capacitance of parallel lines, (2) [...]