capacitance – Page 2 – TechConnect Briefs

Bonding Pad with Reduced Capacity

Mats I., Tarcenco V., Select Techno-Fix Ltd, CA

The technical solutions for the Integrated Circuits (ICs) packaging remains enough conservative during microelectronics development. The ICs with active components having size of micrometers or even nanometers continue to have bonding pads area within hundreds [...]

Microfluidic electromanipulation with capacitive detection for cell diagnostic applications

Ferrier G.A., Hladio A.N., Thomson D.J., Bridges G.E., Hedayatipoor M., Olson S., Freeman M., University of Manitoba, CA

We are proposing an all-electrical approach to mechanical cell diagnostics that uses a combination of electromanipulation for stimulus and capacitance for sensing. We have successfully used the capacitive sensor to detect the electrical trapping (using [...]

Carbon Nanotube Transistors with 60mV/decade Switching and its Capacitance Measurement

Lu Y., Dai H., Nishi Y., Stanford University, US

Recently, we have been able to approach the ultimate vertical scaling limit of carbon nanotube field effect transistors (FETs) and reliably achieve S ~ 60 mV/decade at room temperature, by non-covalent functionalization of single walled [...]

Numerical Capacitance Calculation for Mems Pressure Sensor by Method of Moments

Li P., Weber R.J., Iowa State University, US

MEMS-based capacitive pressure sensors have been widely used in many engineering applications. The design of a MEMS capacitance pressure sensor presents a number of challenges, one of which is the calculation of sensor capacitance and [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Airgap and Line Slope Modeling for Interconnect

Badrieh F., Puchner H., Cypress Semiconductor, US

We have devised a generic methodology for characterizing airgaps and line slope and including those features in interconnect modeling. The method is silicon-based and can be used to accurately model the impact on capacitance. Our [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Unified RLC Model for On-Chip Interconnects

Sim S-P., Yang C., Santa Clara University, US

We present a unified RLC model for deep sub-micron on-chip interconnects. The model consists of two components, a quasi-3D capacitance extraction based on a novel concept of "effective width" and a effective loop inductance model. [...]

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from the Accumulation to Depletion Region

He J., Xi X., Chan M., Cao K., Niknejad A., Hu C., University of California-Berkeley, US

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFETs Operation from Strong Accumulation to Depletion region Jin He*+, Xuemei Xi*, Mansun Chan*, and Chenming Hu* (*Electronics Research Laboratory, Department of Electrical Engineering and Computer [...]

Three-Dimensional Effects Obtained from Capacitance Analysis of an SRAM Cell

Takemura Y., Osada K., Yagyu M., Yamaguchi K., Ushio J., Maruizumi T., Hitachi Ltd., JP

Employing Green's function method, we analyzed the 3D capacitance for the hole interconnect structure in an SRAM cell. We found novel 3D effects as follows; (1) via connection increases the capacitance of parallel lines, (2) [...]