Tenhunen H. – TechConnect Briefs

Low Cost Paper Based Bowtie Tag Antenna for High Performance UHF RFID Applications

Amin Y., Prokkola S., Shao B., Hållstedt J., Chen Q., Tenhunen H., Zheng L-R, Royal Institute of Technology (KTH), SE

In this paper, we have realized a bowtie antenna for UHF RFID Tag with extended round corners for the first time printed on paper substrate. The state of the art CAD tool Ansoft® HFSS is [...]

Nano Scale Autonomous Error-Tolerant (AET) Cellular Network

Liu J., Weerasekera R., Zheng L-R, Tenhunen H., Royal Institute of Technology (KTH), SE

we propose a bottom-up approach using nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture. In our approach, each hexagonal AET cell consists of a nano-core dedicated for local computing, CMOS cell peripherals responsible for cell [...]

Chip Package Co-design of 5GHz RF Receiver Front-End using Multichip Module Technology

Amin S., Amin Y., Tenhunen H., Zheng L-R, Duo X., Amin S., Amin Y., University of Engineering and Technology Taxila, PK

The transceivers for future technology (third generation cellular, wireless LAN) need to be portable (compact), battery-powered and wireless. The present single-chip solutions for RF front-ends do not yield complete system integration. A system-on-a-package (SoP) approach [...]

A Nanocore/CMOS Hybrid System-on-Package (SoP) Architecture for Future Nanoelectronic Systems

Weerasekera R., Liu J., Zheng L-R, Tenhunen H., LECS/IMIT/KTH, SE

We propose Autonomous Error-Tolerant (AET) cellular network based architecture for future nano-electronic systems. Each AET cell consists of a nano-core, dedicated for local computing, CMOS cell-peripherals, responsible for cell I/O and System-level tasks, and their [...]

Electronic Nanotechnology Based on Non-Binary Principles

Mathew J., Dubrova E., Tenhunen H., Royal Institute of Technology, Stockholm, SE

This paper describes alternative to binary number representations and discuss possibilities for implementing multiple-valued functions using chemically assembled electronic nanotechnology. The implementation of a four-valued adder using molecular diodes is presented. The proposed structure is [...]

Logic Optimization and Technology Mapping for CAEN

Färm P., Dubrova E., Tenhunen H., IMIT, KTH, SE

This paper considers the architectures and design issues involved in creating a nano-electronic computing system. We focus on the problems of technology dependent optimization and technology mapping for Chemically Assembled Electronic Nanotechnology (CAEN). We present [...]