Logic Optimization and Technology Mapping for CAEN

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This paper considers the architectures and design issues involved in creating a nano-electronic computing system. We focus on the problems of technology dependent optimization and technology mapping for Chemically Assembled Electronic Nanotechnology (CAEN). We present an experimental tool which optimizes an input circuit description and maps it into a two-dimensional homogeneous array of interconnected molecular logic blocks. The experimental results show that the CPU time of the tool is less than half a second even for quite large benchmarks.

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Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 145 - 148
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Nanoelectronics
ISBN: 0-9728422-1-7